3.0 V to 5.5 V with VIO, 12 kV IEC ESD Protected, Half Duplex 500 kbps RS-485 Transceiver Features: TIA/EIA RS-485 compliant over full supply range 3.0 V to 5.5 V operating voltage range on VCC 1.62 V to 5.5 V VIO logic supply option available ESD protection on the bus pins IEC 61000-4-2 ±12 kV contact discharge IEC 61000-4-2 ≥ ±12 kV air discharge HBM: ≥ ±30 kV Full hot swap support (glitch free power-up/power-down) High speed 50 Mbps data rate (ADM3065E/ADM3066E/ADM3067E/ADM3068E) Low speed 500 kbps data rate for long cables (ADM3061E/ADM3062E/ADM3063E) Full receiver short-circuit, open circuit, and bus idle fail-safe Extended temperature range up to 125°C PROFIBUS compliant at VCC ≥ 4.5 V Half duplex and full duplex models available Allows connection of up to 128 transceivers onto the bus Space-saving package options 10-lead, 3 mm × 3 mm LFCSP 8-lead and 10-lead, 3 mm × 3 mm MSOP 8-lead and 14-lead, narrow body SOIC

3.0 V to 5.5 V with VIO, 12 kV IEC ESD Protected, Half Duplex 500 kbps RS-485 Transceiver Features: TIA/EIA RS-485 compliant over full supply range 3.0 V to 5.5 V operating voltage range on VCC 1.62 V to 5.5 V VIO logic supply option available ESD protection on the bus pins IEC 61000-4-2 ±12 kV contact discharge IEC 61000-4-2 ≥ ±12 kV air discharge HBM: ≥ ±30 kV Full hot swap support (glitch free power-up/power-down) High speed 50 Mbps data rate (ADM3065E/ADM3066E/ADM3067E/ADM3068E) Low speed 500 kbps data rate for long cables (ADM3061E/ADM3062E/ADM3063E) Full receiver short-circuit, open circuit, and bus idle fail-safe Extended temperature range up to 125°C PROFIBUS compliant at VCC ≥ 4.5 V Half duplex and full duplex models available Allows connection of up to 128 transceivers onto the bus Space-saving package options 10-lead, 3 mm × 3 mm LFCSP 8-lead and 10-lead, 3 mm × 3 mm MSOP 8-lead and 14-lead, narrow body SOIC

3.0 V to 5.5 V with VIO, 12 kV IEC ESD Protected, Half Duplex 500 kbps RS-485 Transceiver Features: TIA/EIA RS-485 compliant over full supply range 3.0 V to 5.5 V operating voltage range on VCC 1.62 V to 5.5 V VIO logic supply option available ESD protection on the bus pins IEC 61000-4-2 ±12 kV contact discharge IEC 61000-4-2 ≥ ±12 kV air discharge HBM: ≥ ±30 kV Full hot swap support (glitch free power-up/power-down) High speed 50 Mbps data rate (ADM3065E/ADM3066E/ADM3067E/ADM3068E) Low speed 500 kbps data rate for long cables (ADM3061E/ADM3062E/ADM3063E) Full receiver short-circuit, open circuit, and bus idle fail-safe Extended temperature range up to 125°C PROFIBUS compliant at VCC ≥ 4.5 V Half duplex and full duplex models available Allows connection of up to 128 transceivers onto the bus Space-saving package options 10-lead, 3 mm × 3 mm LFCSP 8-lead and 10-lead, 3 mm × 3 mm MSOP 8-lead and 14-lead, narrow body SOIC

+2.7 V Serial Port RS-232 Transceiver (3 Drivers / 5 Receivers) with 15kV ESD Features: Green Idle power-saving mode  Single 2.7 V to 3.6 V power supply  Operates with 3 V logic  0.1 µF to 1 µF charge pump capacitors  Low EMI  Low power shutdown: 20 nA  Full RS-232 compliance  460 kb/s data rate  One receiver active in shutdown (ADM3307E/ADM3311E/ADM3312E/ADM3315E)  Two receivers active in shutdown (ADM3310E) ESD >15 kV IEC 1000-4-2 on RS-232 I/Os ESD >15 kV IEC 1000-4-2 on CMOS and RS-232 I/Os (ADM3307E)  Qualified for automotive applications

3-V, RS-232 Serial Port Driver-Receiver Features: Green Idle power-saving mode Single 2.7 V to 3.6 V power supply Operates with 3 V logic 0.1 µF to 1 µF charge pump capacitors Low EMI Low power shutdown: 20 nA Full RS-232 compliance 460 kb/s data rate One receiver active in shutdown (ADM3307E/ADM3311E/ADM3312E/ADM3315E) Two receivers active in shutdown (ADM3310E) ESD >15 kV IEC 1000-4-2 on RS-232 I/Os ESD >15 kV IEC 1000-4-2 on CMOS and RS-232 I/Os (ADM3307E) Qualified for automotive applications

Dual, 16-Bit, 2.8 GSPS, TxDAC+ Digital-to-Analog Converter Features: Support input data rate >2 GSPS Proprietary low spurious and distortion design SFDR = 82 dBc at dc IF, −9 dBFS Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Selectable 1×, 2×, 4×, or 8× interpolation filter Low power architecture Transmit enable function allows extra power saving and instant control of the output status High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Low power: 1.42 W at 1.6 GSPS full operating conditions 88-lead LFCSP with exposed pad

Quad, 16-Bit, 2.4 GSPS, TxDAC+ Digital-to-Analog Converter Features: Supports input data rates up to 1 GSPS Proprietary, low spurious and distortion design Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at 180 MHz IF Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at 180 MHz IF SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Input signal power detection High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Digital quadrature modulation using a numerically controlled oscillator (NCO) Nyquist band selection—mix mode Selectable 1×, 2×, 4×, and 8× interpolation filters Low power: 2.11 W at 1.6 GSPS, full operating conditions 88-lead, exposed pad LFCSP

DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84 GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch