1 Watt Power Amplifier SMT, 0.4 - 2.2 GHz Features: Output IP3: +48 dBm 22.5 dB Gain @ 400 MHz 9 dB Gain @ 2100 MHz 53% PAE @ +31 dBm Pout +24 dBm CDMA2000 Channel Power@ -45 dBc ACP Single +5V Supply Integrated Power Control (VPD) QSOP16G SMT Package: 29.4 mm²

1 dB LSB GaAs MMIC 3-Bit Digital Positive Control Attenuator, DC-6 GHz Features: 1 dB LSB Steps to 7 dB High IP3: +55 dBm ±0.25 dB Typical Bit Error Single Control Line Per Bit Single +5V Supply 16 Lead 3×3 mm SMT Package: 9 mm2

HMC474MP86 / HMC474SC70SiGe, HBT gain block amplifiers, SMT, dc to 6 GHz Features: Gain: 15 dB or 15.5 dB P1dB output power: 8 dB Output third-order intercept points (IP3s): 20 dBm or 22 dBm Cascadable 50 inputs/outputs Single supply: 3 V to 10 V Industry standard SC70 Package

InGaP HBT Divide-by-4 SMT, DC - 18 GHz Features: Ultra Low SSB Phase Noise: -150 dBc/Hz Very Wide Bandwidth Output Power: -4 dBm Single DC Supply: +5V 3x3 mm QFN SMT Package

Medium Power Amplifier Chip, 21 - 32 GHz Features: Output IP3: +33 dBm P1dB: +24 dBm Gain: 16 dB Supply Voltage: +5V 50 Ohm Matched Input/Output Die Size: 2.04 x 1.09 x 0.1 mm

VCO SMT with Fo/2 & Divide-by-4, 8.45 - 9.55 GHz Features: Dual Output: Fo = 8.45 - 9.55 GHz Fo/2 = 4.225 - 4.775 GHz Phase Noise: -116 dBc/Hz @100 kHz Typ. Pout: +13 dBm No External Resonator Needed QFN Leadless SMT Package, 25 mm2

Dual Output Low Noise Amplifier, 0.04 - 0.96 GHz Features: Single-ended or Balanced Output High Output IP3: +27 dBm Low Noise Figure: 3.5 dB Single Positive Supply: +5V 75 Ohm Input

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84 GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel, 11-bit resolution 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1  Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch