12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO Features: Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 1.4 GHz to 1.8 GHz Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Automatic/manual reference holdover and reference switchover modes, with revertive switching Glitch-free switchover between references Automatic recovery from holdover Digital or analog lock detect, selectable Optional zero delay operation Twelve 1.6 GHz LVPECL outputs divided into 4 groups Each group of 3 outputs shares a 1-to-32 divider with phase delay Additive output jitter as low as 225 fs rms Channel-to-channel skew grouped outputs < 16 ps Each LVPECL output can be configured as 2 CMOS outputs (for fOUT ≤ 250 MHz) Automatic synchronization of all outputs on power-up Manual output synchronization available SPI- and I2C-compatible serial control port 64-lead LFCSP Nonvolatile EEPROM stores configuration settings

Low Jitter, DDS-based Clock Generator and Synthesizer Features: Excellent intrinsic jitter performance 200 MHz phase frequency detector inputs 655 MHz programmable input dividers for the phase frequency detector (÷M, ÷N) {M, N = 1 to 16} (bypassable) Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable) 8 programmable phase/frequency profiles 400 MSPS internal DDS clock speed 48-bit frequency tuning word resolution 14-bit programmable phase offset 1.8 V supply for device operation 3.3 V supply for I/O, CML driver, and charge pump output Software controlled power-down 48-lead LFCSP package Programmable charge pump current (up to 4 mA) Dual-mode PLL lock detect 655 MHz CML-mode PECL-compliant output driver

Dual DPLL, Quad Input, 10 Output, Multiservice Line Card Clock Translator and Jitter Cleaner Features:Dual DPLL synchronizes 2 kHz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy referencesComplies with ITU-T G.8262 and Telcordia GR-253Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, and G.825Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppbBoth DPLLs feature a 24-bit fractional divider with 24-bit programmable modulusProgrammable digital loop filter bandwidth: 104 Hz to 1850 HzAutomatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operationProgrammable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)2 differential or 4 single-ended input referencesCrosspoint mux interconnects reference inputs to PLLsSupports embedded (modulated) input/output clock signalsFast DPLL locking modesProvides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXOExternal EEPROM support for autonomous initializationSingle 1.8 V power supply operation with internal regulationBuilt in temperature monitor/alarm and temperature compensation for enhanced zero delay performance

10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 61.5 dBFS at 9.7 MHz input 61.0 dBFS at 200 MHz input SFDR 75 dBc at 9.7 MHz input 73 dBc at 200 MHz input Low power 45 mW at 20 MSPS 76 mW at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.10 LSB Serial port control options Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment

12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter Features: SNR = 64.8 dBFS @ fIN up to 70 MHz @ 250 MSPS ENOB of 10.5 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) SFDR = 80 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) Excellent Linearity DNL = ±0.3 LSB typical INL = ±0.7 LSB typical CMOS outputs Single data port at up to 250 MHz Interleaved dual port @ 1/2 sample rate up to 125 MHz 700 MHz full power analog bandwidth On-chip reference, no external decoupling required Integrated input buffer and track-and-hold Low power dissipation 272 mW @ 170 MSPS 364 mW @ 250 MSPS Programmable input voltage range 1.0 V to 1.5 V, 1.25 V nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code)

14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 VP-P input range) SFDR = 78 dBFS at 172.3 MHz (1.59 VP-P input range) Noise density −153.9 dBFS/Hz (1.59 VP-P input range) −155.6 dBFS/Hz (2.04 VP-P input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 VP-P to 2.04 VP-P (1.59 VP-P typical) 2 GHz usable analog input full power bandwidth >95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity

14-Bit, 3 GSPS, JESD204B, Single Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Support for lane rates up to 16 Gbps per lane 2 W total power at 3 GSPS (default settings) Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation 4 integrated digital downconverters 48-bit NCO 4 cascaded half-band filters Phase coherent NCO switching Up to 4 channels available Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither AEQ-Q100 qualified for automotive applications

12-Bit, 1200 MSPS DACs Features: Pin-compatible family Excellent dynamic performance LVDS data interface with on-chip 100 Ω terminations Built-in self test LVDS sampling integrity LVDS-to-DAC data transfer integrity Low power: 380 mW (IFS = 20 mA; fOUT = 330 MHz) 1.8/3.3 V dual-supply operation Adjustable analog output 8.66 mA to 31.66 mA (RL = 25 Ω to 50 Ω) On-chip 1.2 V reference 160-lead chip scale ball grid array (CSP_BGA) package

12-Bit, 210 MSPS TxDAC D/A Converter Features: High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SNR at 5 MHz output, 125 MSPS: 70 dB Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA Power dissipation: 135 mW at 3.3 V Power-down mode: 15 mW at 3.3 V On-chip 1.2 V Reference CMOS compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP Edge-triggered latches

16-Bit, 100 kSPS, Parallel I/O A/D Converter Features: Fast 16-Bit ADC 100 kSPS Throughput Single 5 V Supply Operation Input Range: ±10 V 100 mW Max Power Dissipation Choice of External or Internal 2.5 V Reference High Speed Parallel Interface On-Chip Clock 28-Lead Skinny DIP, SSOP or SOIC Packages