3V/5V, 1 mW, 2-Channel Differential, 16-Bit Sigma-Delta ADC Features: Two Fully Differential Input Channel ADCs Programmable Gain Front End Gains from 1 to 128 Three-Wire Serial Interface SPI®, QSPI™, MICROWIRE™ and DSP Compatible Schmitt Trigger Input on SCLK Ability to Buffer the Analog Input 2.7 V to 3.3 V or 4.75 V to 5.25 V Operation Power Dissipation 1 mW max @ 3 V Standby Current 8 µA max 16-Lead DIP, 16-Lead SOIC and TSSOP Packages

8-Channel, 24-Bit, Simultaneous Sampling ADC Features: 8-channel, 24-bit simultaneous sampling ADC Single-ended or true differential inputs PGA per channel (gains of 1, 2, 4, and 8) Low dc input current ±4 nA (differential)/±8 nA (single-ended) Up to 128 kSPS ODR per channel Programmable ODRs and bandwidth SRC for coherent sampling Sampling rate resolution up to 15.2 × 10−6 SPS Low latency sinc3 and sinc5 filter paths Adjustable phase synchronization Internal 2.5 V reference Two power modes High resolution mode Low power mode Optimizes power dissipation and performance Low resolution SAR ADC for system and chip diagnostics Power supply Bipolar (±1.65 V) or unipolar (3.3 V) supplies Digital I/O supply: 1.8 V to 3.6 V Performance temperature range: −40°C to +105°C Functional temperature range: −40°C to +125°C Performance Combined ac and dc performance 107 dB SNR/dynamic range at 32 kSPS in high resolution mode (sinc5) −109 dB THD ±8 ppm of FSR INL ±15 μV offset error ±0.1% FS gain error ±10 ppm/°C typical temperature coefficient

Dual 1MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface Features: Dual 12-Bit, 2-Channel ADC Fast Throughput Rate 1 MSPS Specified for VDD of 2.7 V to 5.25 V Low Power: 11.4 mW Max at 1 MSPS with 3 V Supplies 24 mW Max at 1 MSPS with 5 V Supplies Wide Input Bandwidth 70 dB SNR at 300 kHz Input Frequency Onboard Reference 2.5 V Flexible Power/Throughput Rate Management Simultaneous Conversion/Read No Pipeline Delays High-Speed Serial Interface SPI®/QSPI™/ MICROWIRE™/DSP Compatible Shut-Down Mode: µA Max 20-Lead TSSOP Package

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

8-Bit, 1 GSPS, JESD204B, Quad Analog-to-Digital Converter Features:JESD204B (Subclass 1 and Subclass 0) coded serial digital outputs Lane rates up to 15 Gbps 1.6 W total power at 1 GSPS 400 mW per ADC channel SFDR: 71 dBFS at 611 MHz (1.44 V p-p input range) SNR: 48.6 dBFS at 611 MHz (1.44 V p-p input range) SINAD: 48.5 dBFS at 611 MHz (1.44 V p-p input range) 0.9 V, 1.8 V, and 2.5 V dc supply operation No missing codes Internal ADC voltage reference Analog input buffer On-chip dithering to improve small signal linearityFlexible differential input range 1.44 V p-p to 2.16 V p-p (1.44 V p-p default) 1.4 GHz analog input full power bandwidth Fast detect bits for efficient AGC implementation Differential clock input Integer clock divide by 1, 2, 4, or 8 On-chip temperature diode Flexible JESD204B lane configurations

Low Input Bias Current, Wide BW JFET Precision Dual Op Amp Features: Low Noise 6 nV/√Hz Low Offset Voltage: 100 µV Max Low Input Bias Current 10 pA Max Fast Settling: 600 ns to 0.01% Low Distortion Unity Gain Stable No Phase Reversal Dual-Supply Operation: ±5 V to ±13 V

40V, 7A Ideal Diode Features: Reduces Power Dissipation by Replacing a Power Schottky Diode with No External Components Internal 7A, 21mΩ N-Channel MOSFET 15mV Regulated Forward Voltage 20μA Operating Current, 0.8μA Shutdown Wide 0V to 40V Input Range with VCC > 2.75V Fast Turn-On Minimizes Voltage Droop Fast Reverse Recovery Time Minimizes Reverse Transient Current Smooth Switchover in Diode-OR Applications 16-Lead 2mm × 3mm LQFN Package

Ultrathin Low VIN, 2A Buck-Boost Module Regulator Features: Wide Input Voltage Range: 2.6V to 5.5V Adjustable Output Voltage Range: 1.8V to 5.5V 2A of Continuous Output Current with VIN ≥ VOUT (Buck Mode and Buck-Boost Mode); Minimum 1A Continuous Output Current with VIN < VOUT (Boost Mode). Low Ripple Buck-Boost Architecture Programmable Soft-Start and VIN UVLO Burst Mode IQ 15μA for High Efficiency at Light Loads Ultrathin, Small Surface Mount Footprint 3.5mm × 4mm × 1.25mm LGA Package

42V, 5A/7A Peak Synchronous Step-Down Silent Switcher with 2.5A Quiescent Current Features: Silent Switcher® Architecture Ultralow EMI Emissions Optional Spread Spectrum Modulation High Efficiency at High Frequency Up to 96% Efficiency at 1MHz, 12VIN to 5VOUT Up to 95% Efficiency at 2MHz, 12VIN to 5VOUT Wide Input Voltage Range: 3.4V to 42V 5A Maximum Continuous, 7A Peak Transient Output Ultralow Quiescent Current Burst Mode® Operation 2.5µA IQ Regulating 12VIN to 3.3VOUT Output Ripple < 10mVP-P Fast Minimum Switch On-Time: 30ns Low Dropout Under All Conditions: 100mV at 1A Forced Continuous Mode Adjustable and Synchronizable: 200kHz to 3MHz Output Soft-Start and Power Good Small 20-Lead 4mm × 3mm LQFN Package AEC-Q100 Qualified for Automotive Applications

36V 10W No-Opto Isolated Flyback Converter Features: 4V to 36V Input Voltage Range 3.6A, 65V Internal DMOS Power Switch Low Quiescent Current Quasi-Resonant Boundary Mode Operation at Heavy Load Low Ripple Burst Mode® Operation at Light Load Minimum Load < 0.5% (Typ) of Full Output No Transformer Third Winding or Opto-Isolator Required for Output Voltage Regulation Accurate EN/UVLO Threshold and Hysteresis Temperature Compensation for Output Diode Output Short-Circuit Protection Thermally Enhanced 8-Lead SO Package