The AD9218 is a dual 10-bit monolithic sampling analog-to-digital converter with on-chip track-and-hold circuits. The product is low cost, low power, and is small and easy to use. The AD9218 operates at a 105 MSPS conversion rate with outstanding dynamic performance over its full operating range. Each channel can be operated independently.The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and a clock for full operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic.The clock input is TTL/CMOS compatible and the 10-bit digital outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies. User-selectable options offer a combination of power-down modes, digital data formats, and digital data timing schemes. In power-down mode, the digital outputs are driven to a high impedance state.Product Highlights Low Power. Only 275 mW power dissipation per channel at 105 MSPS. Other speed grades proportionally scaled down while maintaining high ac performance.  Pin Compatibility Upgrade. Allows easy migration from 8-bit to 10-bit devices. Pin compatible with the 8-bit AD9288 dual ADC.  Easy to Use. On-chip reference and user controls provide flexibility in system design.  High Performance. Maintains 54 dB SNR at 105 MSPS with a Nyquist input.  Channel Crosstalk. Very low at –75 dBc. 6. Fabricated on an Advanced CMOS Process. Available in a 48-lead low profile quad flat package (7 mm × 7 mm LQFP) specified over the industrial temperature range (−40°C to +85°C).ApplicationsBattery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes I and Q communications Ultrasound equipment

The AD9218 is a dual 10-bit monolithic sampling analog-to-digital converter with on-chip track-and-hold circuits. The product is low cost, low power, and is small and easy to use. The AD9218 operates at a 105 MSPS conversion rate with outstanding dynamic performance over its full operating range. Each channel can be operated independently.The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and a clock for full operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic.The clock input is TTL/CMOS compatible and the 10-bit digital outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies. User-selectable options offer a combination of power-down modes, digital data formats, and digital data timing schemes. In power-down mode, the digital outputs are driven to a high impedance state.Product Highlights Low Power. Only 275 mW power dissipation per channel at 105 MSPS. Other speed grades proportionally scaled down while maintaining high ac performance.  Pin Compatibility Upgrade. Allows easy migration from 8-bit to 10-bit devices. Pin compatible with the 8-bit AD9288 dual ADC.  Easy to Use. On-chip reference and user controls provide flexibility in system design.  High Performance. Maintains 54 dB SNR at 105 MSPS with a Nyquist input.  Channel Crosstalk. Very low at –75 dBc. 6. Fabricated on an Advanced CMOS Process. Available in a 48-lead low profile quad flat package (7 mm × 7 mm LQFP) specified over the industrial temperature range (−40°C to +85°C).ApplicationsBattery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes I and Q communications Ultrasound equipment

The AD9229 is a 50 or 65 MSPS quad 12-bit, analog–to–digital converter with serial LVDS outputs. An on–chip track–and–hold circuit is designed for low cost, low power, small size and ease of use. The product operates up to a 65 MSPS conversion rate and is optimized for outstanding dynamic performance where a small package size is critical.The ADC requires a single +3 V power supply. No external reference or driver components are required for many applications. A separate output power supply pin supports LVDS compatible serial digital output levels.The ADC automatically multiplies up the sample rate clock for the appropriate LVDS serial data rate. This data clock output (DCO) provides operation up to 390 MHz and supports double-data rate operation (DDR). An MSB trigger or Frame clock is also provided to signal a new output byte. Power down is supported, and the ADC consumes 3 mW when enabled.Fabricated on an advanced CMOS process, the AD9229 is available in a 48-pin chip scale 7 mm x 7 mm package (48-LFCSP) specified over the industrial temperature range (–40°C to +85°C).ApplicationsDigital beam forming systems for ultrasound Wireless and wired broadband communications Communication test equipment

The AD9911 is a complete direct digital synthesizer (DDS).This device includes a high speed DAC with excellent widebandand narrowband spurious-free dynamic range (SFDR) as well asthree auxiliary DDS cores without assigned digital-to-analogconverters (DACs). These auxiliary channels are used for spurreduction, multitone generation, or test-tone modulation.The AD9911 is the first DDS to incorporate SpurKillertechnology and multitone generation capability. Multitonemode enables the generation up to four concurrent carriers;frequency, phase and amplitude can be independentlyprogrammed. Multitone generation can be used for systemtests, such as inter-modulation distortion and receiver blockersensitivity. SpurKilling enables customers to improve SFDRperformance by reducing the magnitude of harmoniccomponents and/or the aliases of those harmonic components.Test-tone modulation efficiently enables sine wave modulationof amplitude on the output signal using one of the auxiliaryDDS cores.The AD9911 can perform modulation of frequency, phase, oramplitude (FSK, PSK, ASK). Modulation is implemented bystoring profiles in the register bank and applying data to theprofile pins. In addition, the AD9911 supports linear sweep offrequency, phase, or amplitude for applications such as radarand instrumentation.The DDS acts as a high resolution frequency divider with theREF_CLK as the input and the DAC providing the output. TheREF_CLK input can be driven directly or used in combinationwith an integrated REF_CLK multiplier (PLL). The REF_CLKinput also features an oscillator circuit to support an externalcrystal as the REF_CLK source. The crystal can be used incombination with the REF_CLK multiplier.The AD9911 I/O port offers multiple configurations to providesignificant flexibility. The I/O port offers an SPI-compatiblemode of operation that is virtually identical to the SPI operationfound in earlier Analog Devices DDS products.Flexibility is provided by four data pins (Pin SDIO_0,Pin SDIO_1, Pin SDIO_2, and Pin SDIO_3) that allow fourprogrammable modes of I/O operation.The DAC output is supply referenced and must be terminatedinto AVDD by a resistor and an AVDD center-tapped transformer.The DAC has its own programmable reference to enabledifferent full-scale currents.The DDS core (the AVDD pins and the DVDD pins) is poweredby a 1.8 V supply. The digital I/O interface (SPI) operates at3.3 V and requires that the Pin DVDD_I/O (Pin 49) beconnected to 3.3 V. Applications Agile local oscillator Test and measurement equipment Commercial and amateur radio exciter Radar and sonar Test-tone generation Fast frequency hopping Clock generation

The AD9954 is a direct digital synthesizer (DDS) that uses advanced technology, coupled with an internal high speed, high performance DAC to form a complete, digitally programmable, high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 160 MHz. The AD9954 enables fast frequency hopping coupled with fine tuning of both frequency (0.01 Hz or better) and phase (0.022° granularity).The AD9954 is programmed via a high speed serial I/O port. The device includes static RAM to support flexible frequency sweep capability in several modes, plus a user-defined linear sweep mode of operation. Also included is an on-chip high speed comparator for applications requiring a square wave output. An on-chip oscillator and PLL circuitry provide users with multiple approaches to generate the device’s system clock.The AD9954 is specified to operate over the extended industrial temperature range.Applications Agile LO frequency synthesis Programmable clock generators FM chirp source for radar and scanning systems Automotive radars Test and measurement equipment Acousto-optic device drivers

The AD9957 functions as a universal I/Q modulator and agileupconverter for communications systems where cost, size, powerconsumption, and dynamic performance are critical. TheAD9957 integrates a high speed, direct digital synthesizer(DDS), a high performance, high speed, 14-bit digital-to-analogconverter (DAC), clock multiplier circuitry, digital filters, andother DSP functions onto a single chip. It provides basebandupconversion for data transmission in a wired or wirelesscommunications system.The AD9957 is the third offering in a family of quadraturedigital upconverters (QDUCs) that includes the AD9857 andAD9856. It offers performance gains in operating speed, powerconsumption, and spectral performance. Unlike its predecessors,it supports a 16-bit serial input mode for I/Q baseband data.The device can alternatively be programmed to operate either asa single tone, sinusoidal source or as an interpolating DAC.The reference clock input circuitry includes a crystal oscillator,a high speed, divide-by-two input, and a low noise PLL formultiplication of the reference clock frequency.The user interface to the control functions includes a serial porteasily configured to interface to the SPORT of the Blackfin®DSP and profile pins to enable fast and easy shift keying of anysignal parameter (phase, frequency, or amplitude).Applications HFC data, telephony, and video modems Wireless base station transmissions Broadband communications transmissions Internet telephony

The ADA4004-1/ADA4004-2/ADA4004-4 are 1.8 nV/√Hz precision amplifiers featuring 40 μV offset, 0.7 μV/°C drift, 12 MHz bandwidth, and low 1.7 mA per amplifier supply current.The ADA4004-1/ADA4004-2/ADA4004-4 are designed on the high performance iPolar™ process, enabling improvements such as reduced noise and power consumption, increased speed and stability, and smaller footprint size. Novel design techniques enable the ADA4004-1/ADA4004-2/ADA4004-4 to achieve 1.8 nV/√Hz voltage noise density and a low 6 Hz 1/f noise corner frequency while consuming just 1.7 mA per amplifier. The small package saves board space, reduces cost, and improves layout flexibility.Applications for these amplifiers include high precision controls, PLL filters, high performance precision filters, medical and analytical instrumentation, precision power supply controls, ATE, and data acquisition systems. Operation is fully specified from ±5 V to ±15 V from −40°C to +125°C.The ADA4004-1, ADA4004-2, and ADA4004-4 are members of a growing series of low noise op amps offered by Analog Devices, Inc. (see Table 1).ApplicationsPrecision instrumentationFilter blocksMicrophone preamplifiersIndustrial controlThermocouples and RTDsReference buffers

The ADA4899-1 is an ultralow noise (1 nV/√Hz) and distortion (<−117 dBc @1 MHz) unity-gain stable voltage feedback op amp, the combination of which makes it ideal for 16-bit and 18-bit systems. The ADA4899-1 features a linear, low noise input stage and internal compensation that achieves high slew rates and low noise even at unity gain. The Analog Devices, Inc. proprietary next-generation XFCB process and innovative circuit design enable such high performance amplifiers.The ADA4899-1 drives 100 Ω loads at breakthrough performance levels with only 15 mA of supply current. With the wide supply voltage range (4.5 V to 12 V), low offset voltage (230 μV maxi-mum), wide bandwidth (600 MHz), and slew rate (310 V/μs), the ADA4899-1 is designed to work in the most demanding applications. The ADA4899-1 also features an input bias current cancellation mode that reduces input bias current by a factor of 60.The ADA4899-1 is available in a 3 mm × 3 mm LFCSP and an 8-lead SOIC package. Both packages feature an exposed metal paddle that improves heat transfer to the ground plane, which is a significant improvement over traditional plastic packages. The ADA4899-1 is rated to work over the extended industrial temperature range, −40°C to +125°C.Applications Analog-to-digital drivers Instrumentation Filters IF and baseband amplifiers DAC buffers Optical electronics

The ADF7023 is a very low power, high performance, highly integrated 2FSK/GFSK/OOK/MSK/GMSK transceiver designed for operation in the 862 MHz to 928 MHz and 431 MHz to 464 MHz frequency bands, which cover the worldwide license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. It is suitable for circuit applications that operate under the European ETSI EN300-220, the North American FCC (Part 15), the Chinese short-range wireless regulatory standards, or other similar regional standards. Data rates from 1 kbps to 300 kbps are supported.The transmit RF synthesizer contains a VCO and a low noise fractional-N PLL with an output channel frequency resolution of 400 Hz. The VCO operates at 2× or 4×, the fundamental frequency to reduce spurious emissions. The receive and transmit synthesizer bandwidths are automatically, and independently, configured to achieve optimum phase noise, modulation quality, and settling time. The transmitter output power is programmable from −20 dBm to +13.5 dBm, with automatic PA ramping to meet transient spurious specifications. The part possesses both single-ended and differential PAs, which allows for Tx antenna diversity.The receiver is exceptionally linear, achieving an IP3 specification of −12.2 dBm and −11.5 dBm at maximum gain and minimum gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm at maximum gain and minimum gain, respectively. The receiver achieves an interference blocking specification of 66 dB at ±2 MHz offset and 74 dB at ±10 MHz offset. Thus, the part is extremely resilient to the presence of interferers in spectrally noisy environments. The receiver features a novel, high speed, automatic frequency control (AFC) loop, allowing the PLL to find and correct any RF frequency errors in the recovered packet.A patent pending, image rejection calibration scheme is available through a program download. The algorithm does not require the use of an external RF source nor does it require any user intervention once initiated. The results of the calibration can be stored in nonvolatile memory for use on subsequent power-ups of the transceiver.See data sheet for additional information.Applications Smart metering IEEE 802.15.4g Wireless MBUS Home automation Process and building control Wireless sensor networks (WSNs) Wireless healthcare

The ADF7023 is a very low power, high performance, highly integrated 2FSK/GFSK/OOK/MSK/GMSK transceiver designed for operation in the 862 MHz to 928 MHz and 431 MHz to 464 MHz frequency bands, which cover the worldwide license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. It is suitable for circuit applications that operate under the European ETSI EN300-220, the North American FCC (Part 15), the Chinese short-range wireless regulatory standards, or other similar regional standards. Data rates from 1 kbps to 300 kbps are supported.The transmit RF synthesizer contains a VCO and a low noise fractional-N PLL with an output channel frequency resolution of 400 Hz. The VCO operates at 2× or 4×, the fundamental frequency to reduce spurious emissions. The receive and transmit synthesizer bandwidths are automatically, and independently, configured to achieve optimum phase noise, modulation quality, and settling time. The transmitter output power is programmable from −20 dBm to +13.5 dBm, with automatic PA ramping to meet transient spurious specifications. The part possesses both single-ended and differential PAs, which allows for Tx antenna diversity.The receiver is exceptionally linear, achieving an IP3 specification of −12.2 dBm and −11.5 dBm at maximum gain and minimum gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm at maximum gain and minimum gain, respectively. The receiver achieves an interference blocking specification of 66 dB at ±2 MHz offset and 74 dB at ±10 MHz offset. Thus, the part is extremely resilient to the presence of interferers in spectrally noisy environments. The receiver features a novel, high speed, automatic frequency control (AFC) loop, allowing the PLL to find and correct any RF frequency errors in the recovered packet.A patent pending, image rejection calibration scheme is available through a program download. The algorithm does not require the use of an external RF source nor does it require any user intervention once initiated. The results of the calibration can be stored in nonvolatile memory for use on subsequent power-ups of the transceiver.See data sheet for additional information.Applications Smart metering IEEE 802.15.4g Wireless MBUS Home automation Process and building control Wireless sensor networks (WSNs) Wireless healthcare