RF Amplifier IC WiMAX / WiBro 2.3GHz ~ 2.7GHz 16-QFN (3x3)

Digital Potentiometer ICs 7-BIT RDAC WITH UP/DWN CONTROL

Multiplexer Switch ICs CMOS MULTIPLEXER IC

ADC, 12BIT, 40MSPS, TSSOP-28;

The ADF4002 frequency synthesizer is used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the device can be used as a standalone PFD and charge pump.The ADF4002-EP supports defense and aerospace applications (AQEC standard).

The AD7606C-18 is an 18-bit, simultaneous sampling, analog-to-digital data acquisition system (DAS) with eight channels. Each channel contains analog input clamp protection, a programmable gain amplifier (PGA), a low-pass filter (LPF), and an 18-bit successive approximation register (SAR) analog-to-digital converter (ADC). The AD7606C-18 also contains a flexible digital filter, a low drift, 2.5 V precision reference, a reference buffer to drive the ADC, and flexible parallel and serial interfaces.The AD7606C-18 operates from a single 5 V supply and accommodates the following input ranges when sampling at throughput rates of 1 MSPS for all channels: Bipolar single-ended: ?12.5 V, ?10 V, ?6.25 V, ?5 V, and ?2.5 V Unipolar single-ended: 0 V to 12.5 V, 0 V to 10 V, and 0 V to 5 V Bipolar differential: ?20 V, ?12.5 V, ?10 V, and ?5 VThe input clamp protection tolerates voltages up to ?21 V. The single supply operation, on-chip filtering, and high input impedance eliminate the need for external driver op amps, which require bipolar supplies. For applications with lower throughput rates, the AD7606C-18 flexible digital filter can be used to improve noise performance.In hardware mode, the AD7606C-18 is fully compatible with the AD7608 and AD7609. In software mode, the following advanced features are available: Analog input range selectable per channel with added ranges available High bandwidth mode (220 kHz) selectable per channel Additional oversampling options with an oversampling ratio up to 256 System gain, system offset, and system phase calibration, per channel Analog input open circuit detector Diagnostic multiplexer Monitoring functions (serial peripheral interface (SPI) invalid read and write, cyclic redundancy check (CRC), busy stuck monitor, and reset detection)Note that throughout the data sheet, multifunction pins, such as the RD/SCLK pin, are referred to either by the entire pin name or by a single function of the pin, for example, the SCLK pin, when only that function is relevant.APPLICATIONSPower line monitoringProtective relaysMultiphase motor controlInstrumentation and control systemsData acquisition systems

Dual 1MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface Features: Dual 12-Bit, 2-Channel ADC Fast Throughput Rate 1 MSPS Specified for VDD of 2.7 V to 5.25 V Low Power: 11.4 mW Max at 1 MSPS with 3 V Supplies 24 mW Max at 1 MSPS with 5 V Supplies Wide Input Bandwidth 70 dB SNR at 300 kHz Input Frequency Onboard Reference 2.5 V Flexible Power/Throughput Rate Management Simultaneous Conversion/Read No Pipeline Delays High-Speed Serial Interface SPI®/QSPI™/ MICROWIRE™/DSP Compatible Shut-Down Mode: µA Max 20-Lead TSSOP Package

Up to 1 GHz Dual-SHARC+ DSP w/ Integrated Arm Cortex-A5 Features:SHARC+ Core Infrastructure 800 MHz (max) or 1 GHz (max) Core clock frequency 2x 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedArm Core Infrastructure: 1 GHz Arm Cortex-A5 (with Neon/FPU) 32 kByte/32 kByte L1 Instr./Data Cache 256 kByte L2 CacheMemory 2048 KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices)16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 8x Precision Clock Generators 2x 4-channel PDM Mic Inputs 40 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin / 6-pin 6x I2C,3x UARTs 2x Link Ports 16x General Purpose Timer, 1x General Purpose Counter 3x Watchdog Timers ePPI USB 2.0 HS OTG Controller 10/100 EMAC 10/100/1000 EMAC w/AVB and 1588 2x CAN FD 8-ch 12bit Housekeeping ADC 135 GPIO pins, 40 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball FCBGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

RF AMPLIFIERS;

The ADP5061 charger is fully compliant with USB 3.0 and the USB Battery Charging Specification 1.2 and enables charging via the mini USB VBUS pin from a wall charger, car charger, or USB host port.The ADP5061 operates from a 4 V to 6.7 V input voltage range but is tolerant of voltages up to 20 V. The 20 V voltage tolerance alleviates the concerns about the USB bus spiking during disconnect or connect scenarios.The ADP5061 features an internal FET between the linear charger output and the battery. This permits battery isolation and, hence, system powering under a dead battery or no batteryscenario, which allows for immediate system function on connection to a USB power supply.Based on the type of USB source, which is detected by an external USB detection chip, the ADP5061 can be set to apply the correct current limit for optimal charging and USB compliance.The ADP5061 has three factory programmable digital input/output pins that provide maximum flexibility for different systems. These digital input/output pins permit combinations of features such as, input current limits, charging enable and disable, charging current limits, and a dedicated interrupt output pin. APPLICATIONS Digital still cameras Digital video cameras Single cell Li-Ion portable equipment PDAs, audio, GPS devices Portable medical devices Mobile phones