Quad 10A Supply Current, Low IB, Zero-Drift Operational Amplifier Features: Low Supply Current: 10μA Maximum (per Amplifier) Offset Voltage: 5μV Maximum Offset Voltage Drift: 0.02μV/°C Maximum Input Bias Current: 5pA Typical 50pA Maximum, –40°C to 85°C 150pA Maximum, –40°C to 125°C Integrated EMI Filter (90dB Rejection at 1.8GHz) Shutdown Current: 170nA Maximum (per Amplifier) Rail-to-Rail Input and Output 1.7V to 5.25V Operating Supply Range AVOL: 140dB Typical Low-Charge Power-Up for Duty Cycled Applications Specified Temperature Ranges: –40°C to 85°C –40°C to 125°C SC70, TSOT23, MS8, DFN10, TSSOP14 and QFN16 Packages

1nV/Hz 420MHz GBW, 180V/s, Low Distortion Rail-to-Rail Output Op Amps Features: Ultra Low Voltage Noise: 1nV/√Hz Low Distortion: HD2/HD3<–90dBC at 4VP-P,1MHz into 1kΩ High Slew Rate: 180V/μs GBW = 420MHz –3dB Frequency (AV = +1): 330MHz n Input Common Mode Range Includes Negative Rail Output Swings Rail-to-Rail Supply Current: 5.5mA/Channel Typ Operating Supply Range: 2.8V to 11.75V Input Offset Voltage: 95μV Max Offset Drift :0.4μV/°C Low Power Shutdown Very High Open Loop Gain: 9V/μV (139dB), RL = 1kΩ Operating Temp Range: –40°C to 125°C Single in 8-Lead SOIC, TSOT-23, 2mm × 2mm DFN. Duals in 3mm × 3mm DFN, MS8E

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 400-Ball CSP_BGA Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 10x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 4-ch 12bit Housekeeping ADCs 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

5.5 GHz to 18 GHz, GaAs, pHEMT, MMIC, Medium Power Amplifier Features: High saturated output power: 26 dBm with 24% PAE  High gain: 24 dB typical High output IP3: 36 dBm typical High output P1dB: 25.5 dBm Die size: 2.19 mm × 1.05 × 0.1 mm

Medium Power Amplifier SMT, 12 - 30 GHz Features: Gain: 15 dB Saturated Output Power: +18 dBm Output IP3: +25 dBm Single Positive Supply: +5V @ 100 mA 50 Ohm Matched Input/Output RoHS Compliant 4x4 mm Package

Single Channel, 256-Position, I2C / SPI, Nonvolatile Digital Potentiometer Features: 10 kΩ and 100 kΩ resistance options Resistor tolerance: 8% maximum Wiper current: ±6 mA Low temperature coefficient: 35 ppm/°C Wide bandwidth: 3 MHz Fast start-up time < 75 μs Linear gain setting mode Single- and dual-supply operation Independent logic supply: 1.8 V to 5.5 V Wide operating temperature: −40°C to +125°C 3 mm × 3 mm LFCSP Qualified for automotive applications

Nonvolatile, Quad, 64-Position Digital Potentiometer Features: Nonvolatile Memory Preset Maintains Wiper Settings 4-channel independent programmable 64-position resolution EEMEM restore time: 140 μs typical Full monotonic operation 10 kΩ, 50 kΩ, and 100 kΩ terminal resistance See Data Sheet for Additional Information

2.5 V to 5.5 V, 500 A, 2-Wire Interface Quad Voltage Output 12-Bit DAC in a 10-Lead MicroSOIC Package Features: AD5305: 4 buffered 8-bit DACs in 10-lead MSOP A version: ±1 LSB INL, B version: ±0.625 LSB INL AD5315: 4 buffered 10-bit DACs in 10-lead MSOP A version: ±4 LSB INL, B version: ±2.5 LSB INL AD5325: 4 buffered 12-bit DACs in 10-lead MSOP A version: ±16 LSB INL, B version: ±10 LSB INL 2-wire (I2C®-compatible) serial interface 2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes Power-down to 80 nA @ 3 V, 200 nA @ 5 V  Low power operation: 500 μA @ 3 V, 600 μA @ 5 V Three power-down modes Double-buffered input logic Output range: 0 V to VREF Power-on reset to 0 V Simultaneous update of outputs (LDAC function) Software clear facility Data readback facility On-chip rail-to-rail output buffer amplifiers Temperature range: −40°C to +105°C 

High Bandwidth 12-Bit Parallel Interface Multiplying D/A Converter Features: 2.5 V to 5.5 V supply operation Fast parallel interface (17 ns write cycle) Update rate of 20.4 MSPS INL of ±1 LSB for 12-bit DAC ±10 V reference input 10 MHz multiplying bandwidth Extended temperature range: –40°C to +125°C See data sheet for additional features

Quad, 16-Bit nanoDAC with 5ppm/C On-Chip Reference Features: Low power, smallest pin-compatible, quad nanoDACs  AD5664R: 16 bits AD5644R: 14 bits AD5624R: 12 bits User selectable external or internal reference External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference 10-lead MSOP; 10-lead, 3 mm × 3 mm LFCSP_WD; and 12-ball, 1.665 mm × 2.245 mm WLCSP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Serial interface, up to 50 MHz