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TLV274IPW

Texas Instruments TLV274IPW

TLV3501AIDBVT

Texas Instruments TLV3501AIDBVT

TLV3502AID

Texas Instruments TLV3502AID

TLV3542IDGKT

Texas Instruments TLV3542IDGKT

TLV376IDR

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TLV5638ID

Texas Instruments TLV5638ID

TLV6001RIDBVT

Texas Instruments TLV6001RIDBVT

TLV62080DSGT

Texas Instruments TLV62080DSGT

TPA2016D2YZHT

Texas Instruments TPA2016D2YZHT

TPA2025D1YZGT

Texas Instruments TPA2025D1YZGT

Price $3.26 $1.19 $1.56
RoHS Compliant Compliant Compliant Compliant Compliant Yes Yes Compliant Yes Yes
Lead Status No No No No No Yes Yes No Yes Yes
GBW(Typ)(MHz) 3 200 5.5 1
CMRR(Min)(dB) 65 66 72 60
Iq per channel(Typ)(mA) 0.55 5.2 0.815 0.075 2.25 2
Offset Drift(Typ)(uV/C) 2 4.5 1 2
Rating Catalog Catalog Catalog Catalog Catalog Catalog Catalog Catalog Catalog Catalog
Vn at 1kHz(Typ)(nV/rtHz) 39 7.5 8 28
Package Group SOIC,TSSOP,PDIP SOIC,SOT-23 SOIC,SOT-23 SOIC,VSSOP SOIC,SOT-23 SOIC SC70,SOT-23 WSON DSBGA,QFN DSBGA
Total Supply Voltage(Max)(+5V=5, +/-5V=10) 16 5.5 5.5 5.5
Number of Channels(#) 4 1 2 2 1 1
Package Size mm2 mm2 mm2 mm2 mm2 mm2 mm2 mm2 mm2
Vos (Offset Voltage @ 25C)(Max)(mV) 5 6.5 6.5 10 0.100 4.5
Input Bias Current(Max)(pA) 60 3 76
Architecture CMOS CMOS CMOS CMOS Class D Class D
Approx. Price (US$) 0.42 | 1ku 1.00 | 1ku 1.50 | 1ku 0.77 | 1ku 0.46 | 1ku 5.52 | 1ku 0.17 | 1ku 0.45 | 1ku 1.30 | 1ku 0.80 | 1ku
Total Supply Voltage(Min)(+5V=5, +/-5V=10) 2.7 2.5 2.2 1.8
Slew Rate(Typ)(V/us) 2.1 150 2 0.5
Iq per channel(Max)(mA) 0.66 5 5 6.5 1.2 0.1
Additional Features N/A Cost Optimized,EMI Hardened Cost Optimized Cost Optimized,EMI Hardened
Output Current(Typ)(mA) 7 100 30 15
CMRR(Typ)(dB) 80 80 88 76
Operating Temperature Range(C) -40 to 125,0 to 70 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125,-40 to 85,0 to 70 -40 to 125 -40 to 125 -40 to 85 -40 to 85
Rail-to-Rail In to V-,Out In,Out In,Out In,Out In,Out In,Out
Output Type Push-Pull Push-Pull Buffered Voltage
Input Bias Current (+/-)(Max)(nA) 0.01 0.01
Vs(Max)(V) 5.5 5.5
Special Features N/A N/A N/A Enable,Light Load Efficiency,Output Discharge,Power Good,Pre-Bias Start-Up,Synchronous Rectification,UVLO Fixed
VICR(Max)(V) 5.7 5.7
VICR(Min)(V) -0.2 -0.2
Vs(Min)(V) 2.7 2.7
tRESP Low - to - High(us) 0.0045 0.0045
Sample / Update Rate(MSPS) 0.233
Offset Error(Max)(%) N/A
Interface SPI
Settling Time(s) 1
Priority 1
Resolution(Bits) 12
Internal Reference Drift(Max)(ppm/degC) N/A
Output Range Min.(mA/V) 0
DAC Architecture String
DAC Channels
Output Range Max.(mA/V) 5.1
Reference Type
Gain Error(Max)(%FSR) 0.6
Power Consumption(Typ)(mW) 4.5
Zero Code Error(Typ)(mV) 24
INL(Max)(+/-LSB) 4
Code to Code Glitch(Typ)(nV-sec) 5
Iq(Typ)(mA) 0.03 4.5 2
Switching Frequency(Min)(kHz) 2000
Vout(Max)(V) 4
Duty Cycle(Max)(%) 100
Vout(Min)(V) 0.5
Vin(Max)(V) 6
Type Converter
Regulated Outputs(#) 1
Switching Frequency(Max)(kHz) 2000
Iout(Max)(A) 1
Vin(Min)(V) 2.5
Control Mode Constant on-time (COT)
THD + N @ 1 kHz(%) 1 0.07
PSRR(dB) 80 90
Speaker Channels(Max) Stereo Mono
Iq(Max)(mA) 5.5 5
Pin/Package 16DSBGA, 20QFN 12DSBGA
Analog Supply (V)(Max) 5.5 5.5
Output Power(W) 2.8 1.7
Control Interface I2C GPIO
Analog Supply (V)(Min) 2.5 2.5
Audio Input Type Analog Input Analog Input
Shutdown Current (ISD)(uA) 0.2 0.2
Load(Min)(ohms) 4 4