The receive path consists of two independent, wide bandwidth (BW), direct conversion receivers with state-of-the-art dynamic range. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. RF front-end control and several auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) for the power amplifier (PA) are also integrated.In addition to automatic gain control (AGC), the ADRV9008-1 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time, sigma-delta (?-?) ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing relaxes the requirements of the RF filters compared to traditional intermediate frequency (IF) receivers.The fully integrated phase-locked loop (PLL) provides high per-formance, low power, fractional-N, RF synthesis for the receiver signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multi-chip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9008-1 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9008-1 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to mini-mize power consumption during normal use. The ADRV9008-1 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G FDD, macrocell base stations Wide band active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

The ADTR1107 is a compact, 6 GHz to 18 GHz, front-end IC?with an integrated power amplifier, low noise amplifier (LNA), and a reflective single-pole double-throw (SPDT) switch. These?integrated features make the device ideal for phased array antenna and radar applications. The front-end IC offers 25 dBm of saturated output power (PSAT) and 22?dB small signal gain in?transmit state, and 18 dB small signal gain and 2.5 dB noise figure in receive state. The device has a directional coupler for power detection. The input/outputs (I/Os) are internally matched to 50 ?. The ADTR1107 is supplied in a 5 mm ? 5 mm, 24-terminal, land grid array (LGA) package.Applications Phased array antenna Military radar Weather radar Communication links Electronic warfare

The ADXL203 is a high precision, low power, complete dual-axis accelerometer with signal conditioned voltage outputs, all on a single, monolithic IC. The ADXL203 measures acceleration with a full-scale range of ?1.7 g, ?5 g, or ?18 g. The ADXL203 can measure both dynamic acceleration (for example, vibration) and static acceleration (for example, gravity).The typical noise floor is 110 ?g/?Hz, allowing signals below 1 mg (0.06? of inclination) to be resolved in tilt sensing applications using narrow bandwidths (<60 Hz). The user selects the bandwidth of the accelerometer using Capacitor CX and Capacitor CY at the XOUT and YOUT pins. Bandwidths of 0.5 Hz to 2.5 kHz can be selected to suit the application.The ADXL203 is available in a 5 mm ? 5 mm ? 2 mm, 8-terminal ceramic LCC package.Applications: Platform stabilization/leveling Navigation Alarms and motion detectors High accuracy, 2-axis tilt sensing Vibration monitoring and compensation Abuse event detection

DC1012A-C: Demo Board for the LTC2495 16-Bit 8-/16-Channel ΔΣ ADC with PGA, Easy Drive and I2C Interface

DC1027A - Demo Board for LT5560 0.01MHz to 4GHz Low Power Active Mixer

The AD5371 contains 40 14-bit DACs in a single 80-lead LQFP or 100-ball CSP_BGA. The device provides buffered voltage outputs with a span of 4? the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into five groups of eight DACs. Three offset DACs allow the output range of the groups to be adjusted. Group 0 can be adjusted by Offset DAC 0, Group 1 can be adjusted by Offset DAC 1, and Group 2 to Group 4 can be adjusted by Offset DAC 2.The AD5371 offers guaranteed operation over a wide supply range, with VSS from ?16.5 V to ?4.5 V and VDD from 9 V to 16.5 V. The output amplifier headroom requirement is 1.4 V operating with a load current of 1 mA.The AD5371 has a high speed serial interface that is compatible with SPI, QSPI?, MICROWIRE?, and DSP interface standards and can handle clock speeds of up to 50 MHz. It also has a 100 MHz low voltage differential signaling (LVDS) serial interface.The DAC registers are updated on reception of new data. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register to allow removal of gain and offset errors.Each DAC output is gained and buffered on chip with respect to an external SIGGNDx input. The DAC outputs can also be switched to SIGGNDx via the CLR pin.APPLICATIONS Level setting in automatic test equipment (ATE) Variable optical attenuators (VOA) Optical switches Industrial control systems Instrumentation

The HMC870LC5 is a GaAs MMIC pHEMT Distributed Driver Amplifier packaged in a leadless 5x5 mm surface mount package which operates between DC and 20 GHz. The amplifier provides 17 dB of gain, 8Vp-p saturated output swing and features output swing cross point adjustment. Gain flatness is excellent at ?0.5 dB as well as very low additive RMS jitter of 300 fs for 10 Gbps operation.The HMC870LC5 provides Metro and Long Haul designers with scalable power dissipation for varying output drive requirements. (<0.4W at VOUT = 3.6VP-P and <1W at VOUT = 8.5VP-P) The HMC870LC5 has a very wide supply (VDD) operating range from +3.3V to +7V, and the RF I/Os are internally matched to 50 Ohms.APPLICATIONS 10 Gbps NRZ MZ &?Low V Modulator Driver 10 Gbps RZ Transmission 40 Gbps DQPSK Broadband Gain Block for?Test & Measurement Equipment Military & Space

The HMC561LP3(E) is a x2 active broadband frequency multiplier utilizing GaAs PHEMT technology in a leadless RoHS compliant SMT package. When driven by a +5 dBm signal, the multiplier provides +14 dBm typical output power from 8 to 21 GHz and the Fo and 3Fo isolations are 15 dBc at 16 GHz. The HMC561LP3(E) is ideal for use in LO multiplier chains for Pt to Pt & VSAT Radios yielding reduced parts count vs. traditional approaches.The low additive SSB Phase Noise of -139 dBc/Hz at 100 kHz offset helps maintain good system noise performance. The RoHS packaged HMC561LP3(E) eliminates the need for wire bonding, and allows the use of surface mount manufacturing techniques.APPLICATIONS Clock Generation Applications:? SONET OC-192 & SDH STM-64? Point-to-Point & VSAT Radios? Test Instrumentation? Military & Space

The HMC942LP4E is a x2 active broadband frequency multiplier utilizing GaAs pHEMT technology in a leadless RoHS compliant SMT package. When driven by a +4 dBm signal, the multiplier provides +17 dBm typical output power from 13 to 24.6 GHz. The Fo and 3Fo isolations are >20 dBc at 19 GHz. The HMC942LP4E is ideal for use in LO multiplier chains for Pt-to-Pt & VSAT Radios yielding reduced parts count vs. traditional approaches.APPLICATIONS Clock Generation Applications: SONET OC-192 & SDH STM-64 Point-to-Point & VSAT Radios Test Instrumentation Military & Space Sensors

The AD1836A is a high performance, single-chip codec that provides three stereo DACs and two stereo ADCs using ADI?s patented multibit ?-? architecture. An SPI? port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1836A operates from a 5 V supply, with provision for a separate output supply to interface with low voltage external circuitry. The AD1836A is available in a 52-lead MQFP (PQFP) package.APPLICATIONS Home theater systems Automotive audio systems DVD recorders Set-top boxes Digital audio effects processors