The AD9553 is a phase-locked loop (PLL) based clock translator designed to address the needs of passive optical networks (PON) and base stations. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. The user supplies up to two single-ended input reference signals or one differential input reference signal via the REFA and REFB inputs. The device supports holdover applications by allowing the user to connect a 25 MHz crystal resonator to the XTAL input.The AD9553 is pin programmable, providing a matrix of standard input/output frequency translations from a list of 15 possible input frequencies to a list of 52 possible output frequency pairs (OUT1 and OUT2). The device also has a 3-wire SPI interface, enabling the user to program custom input-to-output frequency translations.The AD9553 output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9553 is implemented in a strictly CMOS process.The AD9553 operates over the extended industrial temperature range of ?40?C to +85?C.APPLICATIONS Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators Extremely flexible frequency translation for SONET/SDH, Ethernet, Fibre Channel, DRFI/DOCSIS, and PON/EPON/GPON Wireless infrastructure Test and measurement (including handheld devices)

The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital converter(ADC) with an on-chip sample-and-hold circuitdesigned for low cost, low power, small size, and ease of use.The product operates at a conversion rate of up to 125 MSPSand is optimized for outstanding dynamic performance and lowpower in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performanceoperation. No external reference or driver components arerequired for many applications.The ADC automatically multiplies the sample rate clock for theappropriate LVDS serial data rate. A data clock output (DCO) forcapturing data on the output and a frame clock output (FCO)for signaling a new output byte are provided. Individual-channelpower-down is supported and typically consumes less than 2 mWwhen all channels are disabled. The ADC contains several featuresdesigned to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digitaltest pattern generation. The available digital test patternsinclude built-in deterministic and pseudorandom patterns, alongwith custom user-defined test patterns entered via the serial portinterface (SPI).The AD9653 is available in a RoHS-compliant, 48-lead LFCSP.It is specified over the industrial temperature range of ?40?C to+85?C.PRODUCT HIGHLIGHTS Small Footprint. Four ADCs are contained in a small, space-saving package. Low power of 163 mW/channel at 125 MSPS with scalable power options. Pin compatible to the AD9253 14-bit quad and AD9633 12-bit quad ADC. Ease of Use. A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirementsAPPLICATIONS Medical ultrasound and MRI High speed imaging Quadrature radio receivers Diversity radio receivers Test equipment

The AD9671 is designed for low cost, low power, small size, andease of use for medical ultrasound applications. It contains eightchannels of a VGA with an LNA, a CW harmonic rejection I/Qdemodulator with programmable phase rotation, an AAF, anADC, and a digital demodulator and decimator for dataprocessing and bandwidth reduction.Each channel features a maximum gain of up to 52 dB, a fullydifferential signal path, and an active input preamplifier termination.The channel is optimized for high dynamic performance andlow power in applications where a small package size is critical.The LNA has a single-ended to differential gain that is selectablethrough the serial port interface (SPI). Assuming a 15 MHz noisebandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNRis 94 dB. In CW Doppler mode, each LNA output drives an I/Qdemodulator that has independently programmable phaserotation with 16 phase settings.Power-down of individual channels is supported to increasebattery life for portable applications. Standby mode allows quickpower-up for power cycling. In CW Doppler operation, theVGA, AAF, and ADC are powered down. The ADC containsseveral features designed to maximize flexibility and minimizesystem cost, such as a programmable clock, data alignment, andprogrammable digital test pattern generation. The digital testpatterns include built-in fixed patterns, built-in pseudorandompatterns, and custom user defined test patterns entered via the SPI.Applications Medical imaging/ultrasound Nondestructive testing (NDT)

The AD9681 is an octal, 14-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and an LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The AD9681 automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. Data clock outputs (DCO?1, DCO?2) for capturing data on the output and frame clock outputs (FCO?1, FCO?2) for signaling a new output byte are provided. Individual channel power-down is supported, and the device typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9681 is available in an RoHS-compliant, 144-ball CSP-BGA. It is specified over the industrial temperature range of ?40?C to +85?C. This product is protected by a U.S. patent.Product Highlights Small Footprint. Eight ADCs are contained in a small, 10 mm ? 10 mm package. Low Power. The device dissipates 110 mW per channel at 125 MSPS with scalable power options. Ease of Use. Data clock outputs (DCO?1, DCO?2) operate at frequencies of up to 500 MHz and support double data rate (DDR) operation. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements. Application Medical imaging Communications receivers Multichannel data acquisition

The AD9695 is a dual, 14-bit, 1300 MSPS/625 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 2 GHz. The ?3 dB bandwidth of the ADC input is 2 GHz. The AD9695 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation filters. The NCO has the option to select up to 16 preset bands over the general-purpose input/output (GPIO) pins, or use a coherent fast frequency hopping mechanism for band selection. Operation of the AD9695 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9695 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9695 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output using either one lane, two lanes, or four lanes, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9695 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI) and or PDWN/STBY pin.The AD9695 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +105?C junction temperature range. This product may be protected by one or more U.S. or international patents.Note that, throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product Highlights Low power consumption per channel. JESD204B lane rate support up to 16 Gbps. Wide, full power bandwidth supports intermediate frequency (IF) sampling of signals up to 2 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, WCDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receiver Instrumentation Oscilloscopes Spectrum analyzers Network analyzers Integrated RF test solutions Radars Electronic support measures, electronic counter measures, and electronic counter-counter measures High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths Hybrid fiber coaxial digital reverse path receivers Wideband digital predistortion

The AD97441 is a 14-bit resolution, wideband, third generation member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9744 offers exceptional ac and dc performance while supporting update rates up to 210 MSPS. The AD9744?s low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 60 mW with a slight degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 15 mW. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a 1.2 V temperature compensated band gap reference have been integrated to provide a complete monolithic DAC solution. The digital inputs support 3 V CMOS logic families. Product Highlights The AD9744 is the 14-bit member of the pin compatible TxDAC family, which offers excellent INL and DNL performance. Data input supports twos complement or straight binary data coding. High speed, single-ended CMOS clock input supports 210 MSPS conversion rate. Low power: Complete CMOS DAC function operates on 135 mW from a 2.7 V to 3.6 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. On-chip voltage reference: The AD9744 includes a 1.2 V temperature compensated band gap voltage reference. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages.Applications Wideband communication transmit channel Direct IFs Base stations Wireless local loops Digital radio links Direct digital synthesis (DDS) Instrumentation

The AD9780 / AD9781 / AD9783 include pin-compatible, high dynamic range, dual digital-to-analog converters (DACs) with 12-/14-/16-bit resolutions, and sample rates of up to 500 MSPS. The devices include specific features for direct conversion transmit applications, including gain and offset compensation, and they interface seamlessly with analog quadrature modulators such as the?ADL5370.A proprietary, dynamic output architecture permits synthesis of analog outputs even above Nyquist by shifting energy away from the fundamental and into the image frequency.Full programmability is provided through a serial peripheral interface (SPI) port. Some pin-programmable features are also offered for those applications without a controller.PRODUCT HIGHLIGHTS Low noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals. Proprietary switching output for enhanced dynamic performance. Programmable current outputs and dual auxiliary DACs provide flexibility and system enhancements.APPLICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX Wideband communications LMDS/MMDS, point-to-point RF signal generators, arbitrary waveform generators

The AD9911 is a complete direct digital synthesizer (DDS).This device includes a high speed DAC with excellent widebandand narrowband spurious-free dynamic range (SFDR) as well asthree auxiliary DDS cores without assigned digital-to-analogconverters (DACs). These auxiliary channels are used for spurreduction, multitone generation, or test-tone modulation.The AD9911 is the first DDS to incorporate SpurKillertechnology and multitone generation capability. Multitonemode enables the generation up to four concurrent carriers;frequency, phase and amplitude can be independentlyprogrammed. Multitone generation can be used for systemtests, such as inter-modulation distortion and receiver blockersensitivity. SpurKilling enables customers to improve SFDRperformance by reducing the magnitude of harmoniccomponents and/or the aliases of those harmonic components.Test-tone modulation efficiently enables sine wave modulationof amplitude on the output signal using one of the auxiliaryDDS cores.The AD9911 can perform modulation of frequency, phase, oramplitude (FSK, PSK, ASK). Modulation is implemented bystoring profiles in the register bank and applying data to theprofile pins. In addition, the AD9911 supports linear sweep offrequency, phase, or amplitude for applications such as radarand instrumentation.The DDS acts as a high resolution frequency divider with theREF_CLK as the input and the DAC providing the output. TheREF_CLK input can be driven directly or used in combinationwith an integrated REF_CLK multiplier (PLL). The REF_CLKinput also features an oscillator circuit to support an externalcrystal as the REF_CLK source. The crystal can be used incombination with the REF_CLK multiplier.The AD9911 I/O port offers multiple configurations to providesignificant flexibility. The I/O port offers an SPI-compatiblemode of operation that is virtually identical to the SPI operationfound in earlier Analog Devices DDS products.Flexibility is provided by four data pins (Pin SDIO_0,Pin SDIO_1, Pin SDIO_2, and Pin SDIO_3) that allow fourprogrammable modes of I/O operation.The DAC output is supply referenced and must be terminatedinto AVDD by a resistor and an AVDD center-tapped transformer.The DAC has its own programmable reference to enabledifferent full-scale currents.The DDS core (the AVDD pins and the DVDD pins) is poweredby a 1.8 V supply. The digital I/O interface (SPI) operates at3.3 V and requires that the Pin DVDD_I/O (Pin 49) beconnected to 3.3 V. Applications Agile local oscillator Test and measurement equipment Commercial and amateur radio exciter Radar and sonar Test-tone generation Fast frequency hopping Clock generation

The AD9956 is Analog Devices?s first AgileRF synthesizer.The device is comprised of a DDS and PLL circuitry. The DDSfeatures a 14-bit DAC operating up to 400 MSPS and a 48-bitfrequency tuning word. The PLL Circuitry includes a phasedetector with scaleable 200 MHz inputs (pre-scalar inputsoperate up to 650 MHz) and digital control over the chargepump current. The device also includes a 650 MHz PECL driverwith programmable slew rates.The AD9956 uses advanced DDStechnology, an internal high-speed, high performance D/Aconverter and an advance phase-detector/charge pumpcombination to enable the synthesis of digitally-programmable,frequency-agile analog output sinusoidal waveforms up to2.7 GHz. The AD9956 is designed to provide fast frequencyhopping and fine tuning resolution (48-bit frequency tuningword). Information is loaded into the AD9956 via a serial I/Oport which has a device write speed of 25 MBit/sec. The AD9956DDS block also supports a user defined linear sweep mode ofoperation.The AD9956 is specified to operate over the extendedautomotive range of ?40?C to +125?C.Applications Agile LO frequency synthesis FM chirp source for radar and scanning systems Automotive radars Test and measurement equipment Acousto-optic device drivers

The ADMV1011 is a compact, gallium arsenide (GaAs) design,monolithic microwave integrated circuit (MMIC), doublesideband (DSB) upconverter in a RoHS compliant packageoptimized for point to point microwave radio designs thatoperates in the 17 GHz to 24 GHz frequency range.The ADMV1011 provides 21 dB of conversion gain with 32 dBcof sideband rejection for the lower sideband and 23 dBc ofsideband rejection for the upper sideband. The ADMV1011uses a radio frequency (RF) amplifier preceded by an inphase/quadrature (I/Q) double balanced mixer, where a driveramplifier drives the local oscillator (LO) with a 2? multiplier.IF1 and IF2 mixer inputs are provided and an external 90?hybrid is needed to select the required sideband. The I/Q mixertopology reduces the need for filtering the unwanted sideband.The ADMV1011 is a much smaller alternative to hybrid styleDSB upconverter assemblies and it eliminates the need for wirebonding by allowing the use of surface-mount manufacturingassemblies.The ADMV1011 upconverter comes in a compact, thermallyenhanced, 4.9 mm ? 4.9 mm LCC package. The ADMV1011operates over the ?40?C to +85?C temperature range.Applications Point to point microwave radios Radars and electronic warfare systems Instrumentation, automatic test equipment