10-Bit, 4 Oversampled SDTV Video Decoder with Deinterlacer Features: Worldwide NTSC/PAL/SECAM color demodulation support One 10-bit analog-to-digital converter (ADC), 4× oversampling per channel for CVBS, Y/C, and YPrPb modes Analog video input channels with on-chip antialiasing filter ADV7280: up to 4 input channels ADV7280-M: up to 8 input channels Video input support for CVBS (composite), Y/C (S-Video), and YPrPb (component) NTSC/PAL/SECAM autodetection Up to 1.47 V common-mode input range solution Excellent common-mode noise rejection capabilities 5-line adaptive 2D comb filter and CTI/DNR video enhancement Adaptive Digital Line Length Tracking (ADLLT), signal processing, and enhanced FIFO management provide mini-time base correction (TBC) functionality See data sheet for additional features

Dual HDMI 1.4 Fast Switching Receiver with 12-Bit, 170 MHz Video and Graphics Digitizer and 3D Comb Filter Decoder Features: Dual HDMI 1.4 fast switching receiver 170 MHz video and graphics digitizer 3D comb filter video decoder SCART fast blank support Adaptive HDMI equalizer Integrated CEC controller HDMI repeater support Advanced VBI data slicer 256-ball, 17 mm × 17 mm BGA package 2:1 HDMI 1.4 225 MHz receiver Xpressview™ fast switching of HDMI ports See data sheet for additional features

3-Axis, 200 g Digital MEMS Accelerometer Features: Low power: as low as 35 µA in measurement mode and 0.1 µA in standby mode at VS = 2.5 V (typical) Power consumption scales automatically with bandwidth Embedded, 32-level FIFO buffer minimizes processor load Bandwidth of up to 1 kHz Bandwidth selectable via serial command Shock event detection Activity/inactivity monitoring Supply voltage range: 2.0 V to 3.6 V I/O voltage range: 1.7 V to VS SPI (3- or 4-wire) and I2C digital interfaces Wide temperature range: −40°C to +85°C 10,000 g shock survival Pb free/RoHS compliant Small and thin: 3 mm × 5 mm × 1 mm LGA packageADXL375-EP supports defense and aerospace applications (AQEC standard)Download ADXL375-EP Data Sheet (pdf)Extended industrial temperature range: −55°C to +105°CControlled manufacturing baseline1 assembly/test site1 fabrication siteProduct change notificationQualification data available on requestV62/ 18612 DSCC Drawing Number

2, 31.76 W, Digital Input, Filterless Stereo Class D Audio Amplifier Features: Digital input stereo, high efficiency Class-D amplifier Operates from a single 4.5 V to 16.5 V supply State-of-the-art, proprietary, filterless - modulation 106.5 dB SNR at PO = 8.1 W, RL = 8 , AV = 19 dB, PVDD = 12 V, A weighted 0.004% THD + N at 5 W into 8 38.5 V rms output voltage noise, f = 20 Hz to 20 kHz, A weighted, PVDD = 16 V, 8 Pop and clickless on and off sequence 2 14.67 W output at 12 V supply to 4 loads at <1% THD + N 2 14.4 W output at 16 V supply to 8 loads at <1% THD + N Mono mode for increased maximum output power 1 49.69 W output at 16 V supply to 2 loads at <1% THD + N Support for low impedance loads As low as 3 Ω/5 μH in stereo mode As low as 2 Ω/5 μH in mono mode High power efficiency 93.8% efficiency into an 8 Ω load 90.6% efficiency into a 4 Ω load 12.34 mA quiescent current with single 12 V PVDD supply Single-supply operation with internal LDOs or option to use an external 5 V and 1.8 V supply for lowest power consumption I2C control and hardware modes with up to 16 pin-selectable slots/addresses Supported sample rates from 8 kHz to 192 kHz with 24-bit resolution Multiple PCM audio serial data formats TDM slave with support for up to 16 devices on a single bus I2S or left justified slave Adjustable full-scale output tailored for many PVDD sources 2- and 3-cell Li-Ion batteries Digital volume control with selectable smooth ramp Automatic power-down function Supply monitoring automatic gain control (AGC) function reduces system brownout Standalone operational mode without I2C Temperature sensor with 1°C step readout via I2C Short-circuit, undervoltage, and thermal protection Thermal early warning Power-on reset PVDD sensing ADC 40-lead, 6 mm × 6 mm LFCSP with thermal pad

Up to 1 GHz Dual-SHARC+ DSP w/ Integrated Arm Cortex-A5 Features:SHARC+ Core Infrastructure 800 MHz (max) or 1 GHz (max) Core clock frequency 2x 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedArm Core Infrastructure: 1 GHz Arm Cortex-A5 (with Neon/FPU) 32 kByte/32 kByte L1 Instr./Data Cache 256 kByte L2 CacheMemory 2048 KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices)16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 8x Precision Clock Generators 2x 4-channel PDM Mic Inputs 40 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin / 6-pin 6x I2C,3x UARTs 2x Link Ports 16x General Purpose Timer, 1x General Purpose Counter 3x Watchdog Timers ePPI USB 2.0 HS OTG Controller 10/100 EMAC 10/100/1000 EMAC w/AVB and 1588 2x CAN FD 8-ch 12bit Housekeeping ADC 135 GPIO pins, 40 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball FCBGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

9 GHz to 12 GHz, GaAs, MMIC, I/Q Downconverter Features: Conversion gain: 11 dB (typical) at IFOUT = 100 MHz Image rejection: 25 dB (typical) at IFOUT = 100 MHz LO to RF isolation: 46 dB (typical) LO to IF isolation: 26 dB (typical) IF output frequency: dc to 3.5 GHz 32-lead, 4.9 mm × 4.9 mm ceramic leadless chip carrier

5.6 GHz to 8.6 GHz, GaAs, MMIC, I/Q Downconverter Features: Conversion gain: 13 dB typical Image rejection: 32 dBc typical Input P1dB compression: −6 dBm typical Input IP3: 3 dBm typical, 6.0 GHz to 8.6 GHz Noise figure: 2 dB typical LO to RF isolation: 48 dBm typical LO to IF isolation: 13 dBm typical RF to IF isolation: 10 dBm typical Amplitude balance: 0.2 dB typical Phase balance: −2° typical RF return loss: 10 dB typical LO return loss: 15 dB typical IF return loss: 15 dB typical Exposed paddle, 4 mm × 4 mm, 24-lead, LFCSP

Low Noise Amplifier SMT, 350 - 550 MHz Features: Noise Figure: ≤1 dB Output IP3: +38 dBm Gain: 17 dB Very Stable Gain vs. Supply & Temp Single Supply: +5V @ 104 mA 50 Ohm Matched Output

Medium Power Amplifier SMT, 5 - 20 GHz Features: Gain: 19 dB Saturated Power: +21 dBm @ 21% PAE Output IP3: +30 dBm Single Supply: +5V @ 114 mA 50 Ohm Matched Input/Output RoHS Compliant 3x3 mm SMT package

GaAs pHEMT MMIC Low Noise Amplifier, DC - 20 GHz Features: Noise Figure: 2.5 dB @ 10 GHz Gain: 14 dB @ 10 GHz P1dB Output Power: +16.5 dBm @ 10 GHz Supply Voltage: +8V @ 75 mA 50 Ohm Matched Input/Output 32 Lead Ceramic 5 x 5 mm SMT Package: 25 mm2