The ADP130 is a low quiescent current, low dropout linear regulator. It is designed to operate in dual-supply mode with an input voltage as low as 1.2 V to increase efficiency and provide up to 350 mA of output current. The low 17 mV dropout voltage at a 100 mA load improves efficiency and allows operation over a wider input voltage range.A dual-supply power solution typically improves conversion efficiency over a single-supply solution because the higher VBIAS supply powers the part, and the lower VIN supply delivers current to the load. The power dissipated in the device is thereby reduced. The ADP130 is optimized for stable operation with small 1 ?F ceramic output capacitors. The ADP130 delivers good transient performance with minimal board area.The ADP130 is available in fixed output voltages ranging from : 0.80 V to 3.0 V.The ADP130 has a typical internal soft start time of 200 ?s. Short-circuit protection and thermal overload protection circuits prevent damage in adverse conditions. The ADP130 is available in a tiny 5-lead TSOT package for the smallest footprint solution to meet a variety of portable power applications.ApplicationsMobile phonesDigital camera and audio devicesPortable and battery-powered equipmentPost dc-to-dc regulationData Sheet, Rev. 0, 8/08

The ADP151 is an ultralow noise, low dropout (LDO) linear regulator that operates from 2.2 V to 5.5 V and provides up to 200 mA of output current. The low 135 mV dropout voltage at 200 mA load improves efficiency and allows operation over a wide input voltage range.Using an innovative circuit topology, the ADP151 achieves ultralow noise performance without the necessity of a bypass capacitor, making the device ideal for noise-sensitive analog and RF applications. The ADP151 also achieves ultralow noise performance without compromising the power supply rejection ratio (PSRR) or transient line and load performance. The low 265 ?A of operating supply current at 200 mA load makes the ADP151 suitable for battery-operated portable equipment.The ADP151 also includes an internal pull-down resistor on the EN input.The ADP151 is specifically designed for stable operation with tiny 1 ?F, ?30% ceramic input and output capacitors to meet the requirements of high performance, space constrained applications.The ADP151 is capable of 16 fixed output voltage options, ranging from 1.1 V to 3.3 V.Short-circuit and thermal overload protection circuits prevent damage in adverse conditions. The ADP151 is available in tiny 5-lead TSOT, 6-lead LFCSP, and 4-ball, 0.4 mm pitch, halide-free WLCSP packages for the smallest footprint solution to meet a variety of portable power application requirements.APPLICATIONS RF, voltage controlled oscillator (VCO), and phase locked loop (PLL) power supplies Mobile phones Digital camera and audio devices Portable and battery-powered equipment Post dc-to-dc regulation Portable medical devices Automotive

The?ADP160?/ ADP161 /?ADP162?/?ADP163?are ultralow quiescentcurrent, low dropout, linear regulators that operate from 2.2 Vto 5.5 V and provide up to 150 mA of output current. The low195 mV dropout voltage at 150 mA load improves efficiency andallows operation over a wide input voltage range.The ADP16x are specifically designed for stable operation withtiny 1 ?F ? 30% ceramic input and output capacitors to meetthe requirements of high performance, space-constrainedapplications.The ADP160 is available in 15 fixed output voltage options,ranging from 1.2 V to 4.2 V. The ADP160 / ADP161 also includea switched resistor to discharge the output automatically when the LDO is disabled. The ADP162 is identical to the ADP160but does not include the output discharge function.The ADP161 and ADP163 are available as a adjustable outputvoltage regulators. They are only available in a 5-lead TSOTpackage. The ADP163 is identical to the ADP161 but does notinclude the output discharge function.Short-circuit and thermal overload protection circuits preventdamage in adverse conditions. The ADP160 and ADP162 areavailable in a tiny 5-lead TSOT and a 4-ball, 0.5 mm pitchWLCSP package for the smallest footprint solution to meet avariety of portable power applications.APPLICATIONS Mobile phones Digital cameras and audio devices Portable and battery-powered equipment Post dc-to-dc regulation Portable medical devices

The?ADP160?/?ADP161?/?ADP162?/ ADP163 are ultralow quiescentcurrent, low dropout, linear regulators that operate from 2.2 Vto 5.5 V and provide up to 150 mA of output current. The low195 mV dropout voltage at 150 mA load improves efficiency andallows operation over a wide input voltage range.The ADP16x are specifically designed for stable operation withtiny 1 ?F ? 30% ceramic input and output capacitors to meetthe requirements of high performance, space-constrainedapplications.The ADP160 is available in 15 fixed output voltage options,ranging from 1.2 V to 4.2 V. The ADP160 / ADP161 also includea switched resistor to discharge the output automatically when the LDO is disabled. The ADP162 is identical to the ADP160but does not include the output discharge function.The ADP161and ADP163 are available as a adjustable outputvoltage regulators. They are only available in a 5-lead TSOTpackage. The ADP163 is identical to the ADP161 but does notinclude the output discharge function.Short-circuit and thermal overload protection circuits preventdamage in adverse conditions. The ADP160 and ADP162 areavailable in a tiny 5-lead TSOT and a 4-ball, 0.5 mm pitchWLCSP package for the smallest footprint solution to meet avariety of portable power applications.APPLICATIONS Mobile phones Digital cameras and audio devices Portable and battery-powered equipment Post dc-to-dc regulation Portable medical devices

The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.By default, the ADC output data is routed directly to the two JESD204B serial output lanes. These outputs are at CML voltage levels. Four modes support any combination of M = 1 or 2 (single or dual converters) and L = 1 or 2 (one or two lanes). For dual ADC mode, data can be sent through two lanes at the maximum sampling rate of 250 MSPS. However, if data is sent through one lane, a sampling rate of up to 125 MSPS is supported. Synchronization inputs (SYNCINB? and SYSREF?) are provided.Flexible power-down options allow significant power savings, when desired. Programmable overrange level detection is supported for each channel via the dedicated fast detect pins.Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.The AD9250 is available in a 48-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.Product Highlights Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC. The configurable JESD204B output block supports up to 5 Gbps per lane. An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock. Support for an optional RF clock input to ease system board design. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. Operation from a single 1.8 V power supply. Standard serial port interface (SPI) that supports various product features and functions such as controlling the clock DCS, power-down, test modes, voltage reference mode, over range fast detection, and serial output configuration.Applications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers I/Q demodulation systems Smart antenna systems Electronic test and measurement equipment Radar receivers COMSEC radio architectures IED detection/jamming systems General-purpose software radios Broadband data applications

The AD9253 is a quad, 14-bit, 80 MSPS/105 MSPS/125 MSPSanalog-to-digital converter (ADC) with an on-chip sample-and-holdcircuit designed for low cost, low power, small size,and ease of use. The product operates at a conversion rate ofup to 125 MSPS and is optimized for outstanding dynamicperformance and low power in applications where a smallpackage size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performanceoperation. No external reference or driver components arerequired for many applications.The ADC automatically multiplies the sample rate clock for theappropriate LVDS serial data rate. A data clock output (DCO) forcapturing data on the output and a frame clock output (FCO)for signaling a new output byte are provided. Individual-channelpower-down is supported and typically consumes less than 2 mWwhen all channels are disabled. The ADC contains several featuresdesigned to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digitaltest pattern generation. The available digital test patternsinclude built-in deterministic and pseudorandom patterns, alongwith custom user-defined test patterns entered via the serial portinterface (SPI).The AD9253 is available in a RoHS-compliant, 48-lead LFCSP.It is specified over the industrial temperature range of ?40?C to+85?C. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Small Footprint. Four ADCs are contained in a small, spacesaving package. Low power of 110 mW/channel at 125 MSPS with scalable power options. Pin compatible to the AD9633 12-bit quad ADC. Ease of Use. A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirementsAPPLICATIONS Medical imaging and nondestructive ultrasound Quadrature radio receivers Diversity radio receivers Optical networking Test equipment

The AD9284 is a dual 8-bit, monolithic sampling, analog-to-digital converter (ADC) that supports simultaneous operation and is optimized for low cost, low power, and ease of use. Each ADC operates at up to a 250 MSPS conversion rate with outstanding dynamic performance.The ADC requires a single 1.8 V supply and an encode clock for full performance operation. No external reference components are required for many applications. The digital outputs are LVDS compatible.The AD9284 is available in a Pb-free, 48-lead LFCSP that is specified over the industrial temperature range of ?40?C to +85?C.PRODUCT HIGHLIGHTS Integrated dual 8-bit , 250 MSPS ADC. Single 1.8 V supply operation with LVDS outputs. Power-down option that is controlled through a pin programmable setting.APPLICATIONS Communications Diversity radio systems I/Q demodulation systems Battery-powered instruments Handheld scope meters Low cost digital oscilloscopes OTS: video over fiber

The AD9434 is a 12-bit monolithic sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltagereference, are included on the chip to provide a complete signal conversion solution. The VREF pin can be used to monitor the internal reference or provide an external voltage reference (external reference mode must be enabled through the SPI port). The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced BiCMOS process, the AD9434 isavailable in a 56-lead LFCSP, specified over the industrial temperature range (?40?C to +85?C). This part is protected under a U.S. patent.APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearizationPRODUCT HIGHLIGHTS High Performance. Maintains 65 dBFS SNR at 500 MSPS with a 250 MHz input. Low Power. Consumes only 660 mW at 500 MSPS. Ease of Use. LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample and hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control. Standard serial port interface supports various product functions, such as data formatting, power-down, gain adjust, and output test pattern generation. The AD9434 is pin compatible with the AD9230, and can be substituted in many applications with minimal design changes.

The AD9508 provides clock fanout capability in a design thatemphasizes low jitter to maximize system performance. Thisdevice benefits applications like clocking data converters withdemanding phase noise and low jitter requirements.There are four independent differential clock outputs, each withvarious types of logic levels available. Available logic typesinclude LVDS (1.65 GHz), HSTL (1.65 GHz), and 1.8 V CMOS(250 MHz). In 1.8 V CMOS output mode, the differential outputbecomes two CMOS single-ended signals. The CMOS outputsare 1.8 V logic levels, regardless of the operating supply voltage.Each output has a programmable divider that can be bypassedor be set to divide by any integer up to 1024. In addition, theAD9508 supports a coarse output phase adjustment betweenthe outputs.The device can also be pin programmed for various fixedconfigurations at power-up without the need for SPI or I2C programming.The AD9508 is available in a 24-lead LFCSP and operates froma either a single 2.5 V or 3.3 V supply. The temperature range is?40?C to +85?C.Applications Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure

The AD9517-11?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.30 GHz to 2.65 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9517-1 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9517-1 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9517-1 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9517-1 is specified for operation over the industrial range of ?40?C to +85?C.Applications Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation 1AD9517 is used throughout the data sheet to refer to all the members of the AD9517 family. However, when AD9517-1 is used, it is refers to that specific member of the AD9517 family.