The ADM202 is a 2-channel RS-232 line driver/receiver pairdesigned to operate from a single 5 V power supply. A highlyefficient on-chip charge pump design permits RS-232 levels tobe developed using charge pump capacitors as small as 0.1 µF.This converter generates ±10 V RS-232 output levels.The ADM202 meets or exceeds the TIA/EIA-232-E and V.28specifications. Fast driver slew rates permit 120 kB operation,and high drive currents allow extended cable lengths.An epitaxial BiCMOS construction minimizes power consumptionto 10 mW and guards against latch-up. Overvoltageprotection is provided, allowing the receiver inputs to withstandcontinuous voltages in excess of ±30 V. In addition, all pinscontain ESD protection to levels greater than 2 kV.The ADM202 is available in a 16-lead PDIP and both narrowand wide 16-lead SOIC packages.Applications Computers Peripherals Modems Printers Instruments

The ADM2xx family of line drivers/receivers is intended for all EIA-232-E and V.28 communications interfaces, especially in applications where ±12 V is not available. The ADM205, ADM211 and ADM213 feature a low power shutdown mode which reduces power dissipation to less than 5 µW making them ideally suited for battery powered equipment. The ADM205 does not require any external components and is particularly useful in applications where printed circuit board space critical. The ADM213 has an active-low shutdown and an active-high receiver enable control. Two receivers of the ADM213 remain active during shutdown. This feature is useful for ring indicator monitoring.All members of the ADM2xx family, except the ADM209, include two internal charge pump voltage converters which allow operation from a single +5 V supply. These converters convert the +5 V input power to the ±10 V required for RS-232 output levels. The ADM209 is designed to operate from +5 V and +12 V supplies. An internal +12 V to −12 V charge pump voltage converter generates the −12 V supply.

The ADM2xxE is a family of robust RS-232 and V.28 interface devices which operates from a single +5 V power supply. These products are suitable for operation in harsh electrical environments and are compliant with the EU directive on EMC (89/336/ EEC). Both the level of emissions and immunity are in compliance. EM immunity includes ESD protection in excess of ±15 kV on all I-O lines (1000-4-2), Fast Transient Burst protection (1000-4-4) and Radiated Immunity (1000-4-3). EM emissions include radiated and conducted emissions as required by Information Technology Equipment EN55022, CISPR22.All devices fully conform to the EIA-232E and CCITT V.28 specifications and operate at data rates up to 230 kbps. Shutdown and Enable control pins are provided on some of the products. The shutdown function on the ADM211E disables the charge pump and all transmitters and receivers. On the ADM213E the charge pump, all transmitters, and three of the five receivers are disabled. The remaining two receivers remain active thereby allowing monitoring of peripheral devices. This feature allows the device to be shut down until a peripheral device begins communication. The active receivers can alert the processor which can then take the ADM213E out of the shutdown mode. Operating from a single +5 V supply, four external 0.1 µF capacitors are required. The ADM206E is available in a 24-pin SO package. The ADM207E and ADM208E are available in 24-pin DIP, SO, SSOP and TSSOP packages. The ADM211E and ADM213E are available in 28-pin SO, SSOP and TSSOP packages. All products are backward compatible with earlier ADM2xx products facilitating easy upgrading of older designs.

The ADM4850 / ADM4851 / ADM4852 / ADM4853 / ADM4854 /ADM4855 / ADM4856 / ADM4857 are differential line transceiverssuitable for high speed, half-duplex and full duplex data communication on multipoint bus transmission lines. Theyare designed for balanced data transmission and comply with EIA Standards RS-485 and RS-422. The ADM4850 / ADM4851 / ADM4852 / ADM4853 are half-duplex transceivers that sharedifferential lines and have separate enable inputs for the driver and receiver. The full duplex ADM4854 / ADM4855 / ADM4856 / ADM4857 transceivers have dedicated differential line driveroutputs and receiver inputs.The devices have a 1/8-unit load receiver input impedance, which allows up to 256 transceivers on one bus. Because only onedriver must be enabled at any time, the output of a disabled or powered down driver is three-stated to avoid overloading the bus.The receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted.This guarantees that the receiver outputs are in a known state before communication begins and when communication ends.The driver outputs are slew rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses.Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit.The devices are fully specified over the commercial and industrial temperature ranges and are available in 8-lead SOIC (ADM4850through ADM4857), 8-lead LFCSP (ADM4850 / ADM4852 / ADM4853), and 8-lead MSOP (ADM4850 only) packages.Applications Low power RS-485 applications EMI sensitive systems DTE to DCE interfaces Industrial control Packet switching Local area networks Level translators

The ADM4850 / ADM4851 / ADM4852 / ADM4853 / ADM4854 /ADM4855 / ADM4856 / ADM4857 are differential line transceiverssuitable for high speed, half-duplex and full duplex data communication on multipoint bus transmission lines. Theyare designed for balanced data transmission and comply with EIA Standards RS-485 and RS-422. The ADM4850 / ADM4851 / ADM4852 / ADM4853 are half-duplex transceivers that sharedifferential lines and have separate enable inputs for the driver and receiver. The full duplex ADM4854 / ADM4855 / ADM4856 / ADM4857 transceivers have dedicated differential line driveroutputs and receiver inputs.The devices have a 1/8-unit load receiver input impedance, which allows up to 256 transceivers on one bus. Because only onedriver must be enabled at any time, the output of a disabled or powered down driver is three-stated to avoid overloading the bus.The receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted.This guarantees that the receiver outputs are in a known state before communication begins and when communication ends.The driver outputs are slew rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses.Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit.The devices are fully specified over the commercial and industrial temperature ranges and are available in 8-lead SOIC (ADM4850through ADM4857), 8-lead LFCSP (ADM4850 / ADM4852 / ADM4853), and 8-lead MSOP (ADM4850 only) packages.Applications Low power RS-485 applications EMI sensitive systems DTE to DCE interfaces Industrial control Packet switching Local area networks Level translators

The ADM485 is a differential line transceiver suitable for high speed bidirectional data communication on multipoint bus transmission lines. It is designed for balanced data transmission and complies with both EIA Standards RS-485 and RS-422. The part contains a differential line driver and a differential line receiver. Both the driver and the receiver may be enabled independently. When disabled, the outputs are tristated.The ADM485 operates from a single +5 V power supply. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. This feature forces the driver output into a high impedance state if during fault conditions a significant temperature increase is detected in the internal driver circuitry.Up to 32 transceivers may be connected simultaneously on a bus, but only one driver should be enabled at any time. It is important, therefore, that the remaining disabled drivers do not load the bus. To ensure this, the ADM485 driver features high output impedance when disabled and also when powered down. This minimizes the loading effect when the transceiver is not being utilized. The high impedance driver output is maintained over the entire common-mode voltage range form -7V to +12 V.The receiver contains a fail safe feature which results in a logic high output state if the inputs are unconnected (floating).The ADM485 is fabricated on BiCMOS, an advanced mixed technology process combining low power CMOS with fast switching bipolar technology. All inputs and outputs contain protection against EDS; all diver outputs feature high source and sink current capability. An epitaxial layer is used to guard against latch-up.The ADM485 features extremely fast switching speeds. Minimal driver propagation delays permit transmission at data rates up to 5 Mbits/s while low skew minimizes EMI interference. The part is fully specified over the commercial and industrial temperature range and is available in an 8-pin DIL/SOIC packages.

The ADM485 is a differential line transceiver suitable for high speed bidirectional data communication on multipoint bus transmission lines. It is designed for balanced data transmission and complies with both EIA Standards RS-485 and RS-422. The part contains a differential line driver and a differential line receiver. Both the driver and the receiver may be enabled independently. When disabled, the outputs are tristated.The ADM485 operates from a single +5 V power supply. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. This feature forces the driver output into a high impedance state if during fault conditions a significant temperature increase is detected in the internal driver circuitry.Up to 32 transceivers may be connected simultaneously on a bus, but only one driver should be enabled at any time. It is important, therefore, that the remaining disabled drivers do not load the bus. To ensure this, the ADM485 driver features high output impedance when disabled and also when powered down. This minimizes the loading effect when the transceiver is not being utilized. The high impedance driver output is maintained over the entire common-mode voltage range form -7V to +12 V.The receiver contains a fail safe feature which results in a logic high output state if the inputs are unconnected (floating).The ADM485 is fabricated on BiCMOS, an advanced mixed technology process combining low power CMOS with fast switching bipolar technology. All inputs and outputs contain protection against EDS; all diver outputs feature high source and sink current capability. An epitaxial layer is used to guard against latch-up.The ADM485 features extremely fast switching speeds. Minimal driver propagation delays permit transmission at data rates up to 5 Mbits/s while low skew minimizes EMI interference. The part is fully specified over the commercial and industrial temperature range and is available in an 8-pin DIL/SOIC packages.

The ADN2830 provides closed loop control of the average optical power of a continuous wave (CW) laser diode (LD) after initial factory setup. The control loop adjusts the laser IBIAS to maintain a constant Back Facet Monitor Photo Diode (MPD) current and hence a constant laser optical power. The external PSET resistor is adjusted during factory set up to set the desired optical power. RPSET is set at 1.23/IAV, where IAVis the MPD current corresponding to the desired optical power. Programmable alarms are provided for laser fail (end of life) and laser degrade (impending fail).The ADN2830 operates from a single power +5 V supply. It is available in 5mm × 5mm LFCSP-32 Lead Frame Chip Scale.

The ADN2892 is a 4.25 Gbps limiting amplifier with integratedloss of signal (LOS) detection circuitry and a received signalstrength indicator (RSSI). This part is optimized for FibreChannel (FC) and Gigabit Ethernet (GbE) optoelectronicconversion applications. The ADN2892 has a differential inputsensitivity of 3.5 mV p-p and accepts up to a 2.0 V p-pdifferential input overload voltage. The ADN2892 has currentmode logic (CML) outputs with controlled rise and fall times.The ADN2892 has a selectable low-pass filter with a −3 dBcutoff frequency of 1.5 GHz. By setting BW_SEL to Logic 0, thefilter can limit the relaxation oscillation of a low cost CD laserused in a legacy 1 Gbps FC transmitter. The limited BW alsoreduces the rms noise and in turn improves the receiver opticalsensitivity for a lower data rate application, such as 1× FC andGbE.By monitoring the bias current through a photodiode, the onchipRSSI detector measures the average power received with2% typical linearity over the entire valid input range of thephotodiode. The on-chip RSSI detector facilitates SFF-8472-compliant optical transceivers by eliminating the need forexternal RSSI detector circuitry.Additional features include a programmable loss-of-signal(LOS) detector and output squelch. The ADN2892 is availablein a 3 mm × 3 mm, 16-lead LFCSP.Applications 1×, 2×, and 4× FC transceivers  SFP/SFF/GBIC optical transceivers  GbE transceivers  Backplane receivers

ADP7104 20 V, 500 mA, Low Noise, CMOS LDOThe ADP3334 is a member of the ADP333x family of precision low dropout anyCAP® voltage regulators. The ADP3334 operates with an input voltage range of 2.6 V to 11 V and delivers a continuous load current up to 500 mA. The novel anyCAP® architecture requires only a very small 1 µF output capacitor for stability, and the LDO is insensitive to the capacitor’s equivalent series resistance (ESR). This makes ADP3334 stable with any capacitor, including ceramic (MLCC) types for space restricted applications.