10 MHz, 14.5 nV/Hz, Rail-to-Rail I/O, Zero Input Crossover Distortion Amplifier Features: Power supply rejection ratio (PSRR): 98 dB minimum  Common-mode rejection ratio (CMRR): 95 dB minimum Offset voltage: 120 μV maximum Single-supply operation: 2.7 V to 5.5 V  Dual-supply operation: ±1.35 V to ±2.75 V  Wide bandwidth: 10 MHz  Rail-to-rail input and output  Low noise 2 μV p-p from 0.1 Hz to 10 Hz  14.5 nV/√Hz at 1 kHz  Very low input bias current: 2 pA maximum

Eval Board, Digital Time Delay Rohs Compliant: Yes |Analog Devices 127102-HMC856LC5

The ADSP-21062 and ADSP-21060 SHARC DSPs are signal processing microcomputers that offer new capabilities and levels of performance. The ADSP-2106x SHARCs are 32-bit processors optimized for high performance DSP applications. The ADSP-2106x builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus. Fabricated in a high speed, low power CMOS process, the ADSP-2106x has a 25 ns instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle.The ADSP-2106x SHARC DSP represents a new standard of integration for signal computers, combining a high performance floating-point DSP core with integrated, on-chip system features including a 4 Mbit SRAM memory (2 Mbit on the ADSP-21062, 1 Mbit on the ADSP-21061), host processor interface, DMA controller, serial ports, and link port and parallel bus connectivity for glueless DSP multiprocessing.

Data Conversion IC Development Tools LTC1867CGN Demo Board 16-Bit, 8-Channel 200ksps ADC (req DC2026)

RF Switch ICs GaAs MMIC SP4T Non-Reflective Switch,

The ADF7241 is a highly integrated, low power, and high performance transceiver for operation in the global 2.4 GHz ISM band. It is designed with emphasis on flexibility, robustness, ease of use, and low current consumption. The IC supports the IEEE 802.15.4-2006 2.4 GHz PHY requirements in both packet and data streaming modes. With a minimum number of external components, it achieves compliance with the FCC CFR47 Part 15, ETSI EN 300 440 (Equipment Class 2), ETSI EN 300 328 (FHSS, DR > 250 kbps), and ARIB STD T-66 standards.The ADF7241 complies with the IEEE 802.15.4-2006 2.4 GHz PHY requirements with a fixed data rate of 250 kbps and DSSS-OQPSK modulation. The transmitter path of the ADF7241 is based on a direct closed-loop VCO modulation scheme using a low noise fractional-N RF frequency synthesizer. The automatically calibrated VCO operates at twice the fundamental frequency to reduce spurious emissions and avoid PA pulling effects. The bandwidth of the RF frequency synthesizer is automatically optimized for transmit and receive operations to achieve best phase noise, modulation quality, and synthesizer settling time performance. The transmitter output power is programmable from ?20 dBm to +4 dBm with automatic PA ramping to meet transient spurious specifications. An integrated biasing and control circuit is available in the IC to significantly simplify the interface to external PAs.For more information, please refer to the data sheet.Applications Wireless sensor networks Automatic meter reading/smart metering Industrial wireless control Healthcare Wireless audio/video Consumer electronics ZigBee

The AD9576 provides a multiple output clock generator function comprising two dedicated phase-locked loop (PLL) cores with flexible frequency translation capability, optimized to serve as a robust source of asynchronous clocks for an entire system, providing extended operating life within frequency tolerance through monitoring of and automatic switchover between redundant crystal (XTAL) inputs with minimized switching, induced transients. The fractional-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance, whereas the integer-N PLL provides general-purpose clocks for use as CPU and field-programmable gate array (FPGA) reference clocks.The AD9576 uses pin strapping to select among a multitude of power-on ready configurations for its 11 output clocks, which require only the connection of external pull-up or pull-down resistors to the appropriate pin program reader pins (PPRx). These pins provide control of the internal dividers for establishing the desired frequency translations, clock output functionality, and input reference functionality. These parameters can also be manually configured through a serial port interface (SPI).The AD9576 is packaged in a 64-lead, 9 mm ? 9 mm LFCSP, requiring only a single 2.5 V or 3.3 V supply. The operating temperature range is ?40?C to +85?C.Each OUTx output is differential and contains two pins: OUTx and OUTx. For simplicity, the term OUTx refers to the functional output block containing these two pins..Applications Ethernet line cards, switches, and routers Baseband units SATA and PCI express Low jitter, low phase noise clock generation Asynchronous clock generation

ANALOG SWITCH SINGLE SPDT SC-70-6 FULL REEL; Analog Switch Type:SPDT; No. of Channels:1Channels; On State Resistance Max:2.5ohm; Supply Voltage Range:1.8V to 5.5V; Analog Switch Case:SC-70; No. of Pins:6Pins; Product Range:-

LDO VOLTAGE REGULATORS;

Demonstration Circuit 1598A is a fixed frequency synchronous buck-boost converter with an extended input and output range. The unique 4-switch, single inductor architecture provides low noise and seamless operation from input voltages above, below, or equal to the output voltage. The LTC3112 features selectable PWM or Burst Mode operation, and an easily synchronizable oscillator. An output current monitor allows the load current to be controlled or monitored. The LTC3112 operates with a 2.7V to 15V input voltage range and a VOUT range from 2.5V to 14V. The demonstration board has been designed to operate with VIN from 2.7V to 15V and an output current up to 2.5A. For VIN < 5V, IOUT capability is reduced. VOUT is set to 5.0V.