Quad, 16-Bit nanoDAC with 5ppm/C On-Chip Reference Features: Low power, smallest pin-compatible, quad nanoDACs  AD5664R: 16 bits AD5644R: 14 bits AD5624R: 12 bits User selectable external or internal reference External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference 10-lead MSOP; 10-lead, 3 mm × 3 mm LFCSP_WD; and 12-ball, 1.665 mm × 2.245 mm WLCSP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Serial interface, up to 50 MHz

Quad, 12-Bit nanoDAC+ with SPI Interface Features: High relative accuracy (INL): ±1 LSB maximum @ 12 bits Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility 50 MHz SPI with readback or daisy chain Low glitch: 0.5 nV-sec Low power: 1.8 mW at 3 V 2.7 V to 5.5 V power supply −40°C to +105°C temperature range

Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers Features: Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS/channel (161 µs settling) Performance specifications 17.2 noise free bits at 31.25 kSPS 24 noise free bits at 5 SPS INL: ±2 ppm of FSR 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 2 fully differential channels or 4 single-ended channels Crosspoint multiplexer On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers Internal or external clock See data sheet for additional features

8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: 3 power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification) Crosspoint multiplexed analog inputs 8 differential/15 pseudo differential inputs See data sheet for additional features

4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: Three power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator On-chip bias voltage generator Low-side power switch General-purpose outputs Multiple filter options Internal temperature sensor Self and system calibration Sensor burnout detection Automatic channel sequencer Per channel configuration Power supply: 2.7 V to 3.6 V and ±1.8 V Independent interface power supply Power-down current: 5 μA maximum Temperature range: −40°C to +125°C 32-lead LFCSP/24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ESD: 4 kVAD7124-4-EP Supports defense and aerospace applications (AQEC standard) Download AD7124-4-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19614

16-Bit, 750 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC Features: Multiple pins/software programmable input ranges: 5 V, 10 V, ±5 V, ±10 V Pins or serial SPI®-compatible input ranges/mode selection Throughput 750 kSPS (warp mode) 600 kSPS (normal mode) 500 kSPS (impulse mode) INL: ±0.75 LSB typical, ±1.5 LSB maximum (±23 ppm of FSR) 16-bit resolution with no missing codes SNR: 92 minimum (5 V) @ 2 kHz, 94 dB typical (±10 V) @ 2 kHz THD: −107 dB typical iCMOS™ process technology 5 V internal reference: typical drift 3 ppm/°C; TEMP output No pipeline delay (SAR architecture) Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible

18-Bit, 1.25 MSPS PulSAR A/D Converter Features: Throughput: 1.25 MSPS INL: ±2 LSB typical, ±3 LSB max; ±8 ppm of full scale 18-bit resolution with no missing codes Dynamic range: 95.5 dB SINAD: 93.5 dB typical @ 20 kHz (VREF = 2.5 V) THD: −112 dB typical @ 20 kHz (VREF = 2.5 V) No pipeline delay (SAR architecture) Pb-free, 48-lead LQFP and 48-lead LFCSP Pin compatible with the AD7641 and other PulSAR ADCs 2.048 V internal reference: typical drift 10 ppm/°C; TEMP output Differential input range: ±VREF (VREF up to 2.5 V) Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface SPI®/QSPI™/MICROWIRE™/DSP compatible Single 2.5 V supply operation Power dissipation 65 mW typical @ 1.25 MSPS with internal REF 2 W in power-down mode

16-Bit, 8-Channel,250 kSPS PulSAR ADC Features: Download AD7689-KGD Data Sheet. Available as Known Good Die and fully guaranteed to data sheet specifications. 16-bit resolution with no missing codes 4-channel (AD7682)/8-channel (AD7689) multiplexer with choice of inputs Unipolar single-ended Differential (GND sense) Pseudobipolar Throughput: 250 kSPS INL: ±0.4 LSB typical, ±1.5 LSB maximum (±23 ppm or FSR) Dynamic range: 93.8 dB SINAD: 92.5 dB at 20 kHz THD: −100 dB at 20 kHz Analog input range: 0 V to VREF with VREF up to VDD Multiple reference types Internal selectable 2.5 V or 4.096 V External buffered (up to 4.096 V) External (up to VDD) Internal temperature sensor (TEMP) Channel sequencer, selectable 1-pole filter, busy indicator No pipeline delay, SAR architecture Single-supply 2.3 V to 5.5 V operation with 1.8 V to 5.5 V logic interface Serial interface compatible with SPI, MICROWIRE, QSPI, and DSP Power dissipation 3.5 mW at 2.5 V/200 kSPS 12.5 mW at 5 V/250 kSPS Standby current: 50 nA Low cost grade available 20-lead 4 mm × 4 mm LFCSP package 20-lead 2.4 mm × 2.4 mm WLCSP package

3V/5V, 1 mW, 2-Channel Differential, 16-Bit Sigma-Delta ADC Features: Two Fully Differential Input Channel ADCs Programmable Gain Front End Gains from 1 to 128 Three-Wire Serial Interface SPI®, QSPI™, MICROWIRE™ and DSP Compatible Schmitt Trigger Input on SCLK Ability to Buffer the Analog Input 2.7 V to 3.3 V or 4.75 V to 5.25 V Operation Power Dissipation 1 mW max @ 3 V Standby Current 8 µA max 16-Lead DIP, 16-Lead SOIC and TSSOP Packages

3V/5V, 1 mW, 2-Channel Differential, 16-Bit Sigma-Delta ADC Features: Two Fully Differential Input Channel ADCs Programmable Gain Front End Gains from 1 to 128 Three-Wire Serial Interface SPI®, QSPI™, MICROWIRE™ and DSP Compatible Schmitt Trigger Input on SCLK Ability to Buffer the Analog Input 2.7 V to 3.3 V or 4.75 V to 5.25 V Operation Power Dissipation 1 mW max @ 3 V Standby Current 8 µA max 16-Lead DIP, 16-Lead SOIC and TSSOP Packages