Accelerometers High Perf 3-Axis Digit +/-2g/+/-4g/+/-8g Accel

High Speed Operational Amplifiers HIGH PERFORMANCE RRIO

Dual 12-Bit nanoDAC with 5 ppm/C On-Chip Reference Features: Low power, smallest pin-compatible, dual nanoDAC AD5663R: 16 bits AD5643R: 14 bits AD5623R: 12 bits User-selectable external or internal reference External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference 10-lead MSOP and 3 mm × 3 mm LFCSP 2.7 V to 5.5 V power supply Guaranteed monotonic by design See data sheet for additional featuresAD5623R-EP supports defense and aerospace applications (AQEC standard) Download AD5623R-EP Data Sheet (pdf) Extended temperature range: −55°C to +105°C Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/14633-01XE DSCC Drawing Number

Low Cost, High Speed, Rail-to-Rail Amplifier Features: High speed and fast settling on 5 V 110 MHz, −3 dB bandwidth (G = +1) (AD8051/AD8052) 150 MHz, −3 dB bandwidth (G = +1) (AD8054) 145 V/μs slew rate 50 ns settling time to 0.1% Single-supply operation Output swings to within 25 mV of either rail Input voltage range: −0.2 V to +4 V; VS = 5 V Video specifications (G = +2) 0.1 dB gain flatness: 20 MHz; RL = 150 Ω Differential gain/phase: 0.03%/0.03° Low distortion −80 dBc total harmonic @ 1 MHz, RL = 100 Ω Outstanding load drive capability Drives 45 mA, 0.5 V from supply rails (AD8051/AD8052) Drives 50 pF capacitive load (G = +1) (AD8051/AD8052) Low power: 2.75 mA/amplifier (AD8054) Low power: 4.4 mA/amplifier (AD8051/AD8052)

Dual, 14-Bit, 1230 MSPS, TxDAC+ Digital-to-Analog Converter Features: Flexible LVDS interface allows word or byte load Single-carrier W-CDMA ACLR = 82 dBc at 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Integrated 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth Gain, dc offset, and phase adjustment for sideband suppression Multiple chip synchronization interfaces High performance, low noise PLL clock multiplier Digital inverse sinc filter Low power: 1.5 W at 1.2 GSPS, 800 mW at 500 MSPS, full operating conditions 72-lead, exposed paddle LFCSP

Analog to Digital Converters - ADC 1.8V 12Bit 80 Msps ADC

Analogue Switch ICs 1.8V to 5.5V 2:1 Mux/SPDT Switch I.C.

Isolated Module DC DC Converter 2 Output 2.5 ~ 13V 1.2 ~ 12V 440mA, 300mA 3.1V - 32V Input

Current Source Regulator 10mA 8-SOIC

Micropower 3-Sensor Combination Including Acceleration and Temperature Features: All sensors sampled synchronously Up to 400 Hz ODR Samples can be synchronized to external trigger Ultralow power 1.95 A at 100 Hz ODR, 2.0 V supply, all sensors on 270 nA at 6 Hz motion activated wake-up mode 10 nA standby current 12-bit resolution for all sensors Acceleration scale factor down to 1 mg/LSB Temperature scale factor: 0.065C/LSB (typical) Built-in features for motion-based system level power savings Adjustable threshold sleep/wake modes for motion activation Accelerometer, temperature sensor, and provision for third analog sensor input Autonomous interrupt processing, without need for microcontroller intervention, to allow the rest of the system to be turned off completely Deep embedded FIFO minimizes host processor load Awake state output enables implementation of standalone, motion activated switch Wide supply and I/O voltage ranges: 1.6 V to 3.5 VOperates off 1.8 V to 3.3 V railsPower can be derived from coin cell batterySPI digital interfaceSmall and thin 3 mm 3.25 mm 1.06 mm package