8-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP Features: Fast throughput rate: 1 MSPS Specified for AVDD of 2.7 V to 5.25 V Low Power: 6.0 mW max at 1 MSPS with 3 V supply 13.5 mW max at 1 MSPS with 5 V supply Eight (single-ended) inputs with sequencer Wide input bandwidth: AD7928, 70 dB min SINAD at 50 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible

High Current Output, Triple Video Amplifier Features: Drives 13 V Output Drives Unlimited Capacitive Load High Current Output Drive: 70 mA Excellent Video Specifications (RL = 150 Ω) Gain Flatness 0.1 dB to 10 MHz 0.06% Differential Gain Error 0.02° Differential Phase Error Power Operates on ±2.5 V to ±7.5 V Supply 10.0 mA/Amplifier Max Power Supply Current High Speed 250 MHz Unity Gain Bandwidth (3 dB) 1200 V/µs Slew Rate Fast Settling Time of 35 ns (0.1%) High Speed Disable Function Turn-Off Time 30 ns Easy to Use 200 mA Short Circuit Current Output Swing to 1 V of Rails

Broadband Modem Mixed-Signal Front End Features: Low cost, 3.3 V CMOS MxFE® for broadband modems 10-bit digital-to-analog converter (DAC) 2×/4× interpolation filter 250 MSPS DAC update rate 10-bit, 75 MSPS ADC Low noise RxPGA Dual channel muxed input 6 dB input overload attenuator −12 dB to +48 dB (without attenuator) Third-order programmable low-pass filter Flexible digital datapath interface Half-duplex and full-duplex operation Programmable delay Tx driver disable signal Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs 64-lead LFCSP

High Performance 8-Bit Display Interface Features: 8-bit analog-to-digital converters 140 MSPS maximum conversion rate Low PLL clock jitter at 140 MSPS Automatic gain matching Automated offset adjustment 2:1 input mux Power-down via dedicated pin or serial register 4:4:4, 4:2:2, and DDR output format modes Variable output drive strength Odd/even field detection External clock input Regenerated Hsync output

110 MSPS/140 MSPS Analog Interface for Flat Panel Displays Features: Automated clamping level adjustment 140 MSPS maximum conversion rate 300 MHz analog bandwidth 0.5 V to 1.0 V analog input range 500 ps p-p PLL clock jitter at 110 MSPS 3.3 V power supply Full sync processing Sync detect for hot plugging Midscale clamping Power-down mode Low power: 500 mW typical 4:2:2 output format mode

High Speed, 5 V, 0.1 F CMOS RS-232 Driver/Receiver Features: 120 kB transmission rate Small (0.1 µF) charge pump capacitors Single 5 V power supply Meets TIA/EIA-232-E and V.28 specifications 2 drivers and 2 receivers On-board dc-to-dc converters ±9 V output swing with 5 V supply Low power BiCMOS: 2.5 mA ICC ±30 V receiver input levels

Equalisers Front Panel HDMI Buffer - TMDS Only

Operational Amplifiers - Op Amps VLTG-FDBK, G= 2 CLAMP AMP

Charge Pump, 7-Channel Smart LED Driver with I2C Interface Features: Charge pump with automatic gain selection of 1×, 1.5×, and 2× for maximum efficiency 7 independent, programmable LED drivers 7 drivers capable of 30 mA (typical) 1 driver also capable of 60 mA (typical) Programmable maximum current limit (128 levels) Standby mode for <1 μA current consumption 16 programmable fade in and fade out time 0.1 sec to 5.5 sec Choose from linear, square, or cubic rates Fading override I2C-compatible interface for all programming Dedicated reset pin and built-in power-on reset (POR) Short-circuit, overvoltage, and overtemperature protection Internal soft start to limit inrush currents Input-to-output isolation during faults or shutdown Operation down to VIN = 2.5 V with undervoltage lockout (UVLO) at VIN = 2.0 V Available in a small 20-ball, 2.15 mm × 2.36 mm × 0.6 mm WLCSP or a 20-lead, 4 mm × 4 mm × 0.75 mm LFCSP

Precision Amplifiers Aual 1 A CMOS OpAmp