16-Channel, 16-Bit Voltage Output denseDAC Features: Download AD5766-KGD Data Sheet. Available as Known Good Die and fully guaranteed to data sheet specifications. Complete 16-channel, 16-bit DACs 8 software-programmable output ranges: −20 V to 0 V, −16 V to 0 V, −10 V to 0 V, −10 V to +6 V, −12 V to +14 V, −16 V to +10 V, ±5 V and ±10 V Integrated DAC output buffers with ±20 mA output current capability 4 mm × 4 mm WLCSP package and 40-lead LFCSP package Integrated reference buffers 2 dither signal input pins Channel monitoring multiplexer 1.8 V logic compatibility Temperature range: −40°C to +105°C

High Precision, Impedance & Electrochemical Front End Features: Analog input 16-bit ADC with both 800 kSPS and 1.6 MSPS options Voltage, current, and impedance measurement capability Internal and external current and voltage channels Ultralow leakage switch matrix and input mux Input buffers and programmable gain amplifier Voltage DACs Dual output voltage DAC with an output range of 0.2 V to 2.4 V 12-bit VBIAS0 output to bias potentiostat 6-bit VZERO0 output to bias TIA Ultra low power: 1 µA 1 high speed, 12-bit DAC Output range to sensor: ±607 mV Programmable gain amplifier on output with gain settings of 2 and 0.05 Amplifiers, accelerators, and references 1 low power, low noise potentiostat amplifier suitable for potentiostat bias in electrochemical sensing 1 low noise, low power TIA, suitable for measuring sensor current output 50 pA to 3 mA range Programmable load and gain resistors for sensor output Analog hardware accelerators Digital waveform generator Receive filters Complex impedance measurement (DFT) engine 1 high speed TIA to handle wide bandwidth input signals from 0.015 Hz up to 200 kHz Digital waveform generator for generation of sinusoid and trapezoid waveforms 2.5 V and 1.82 V internal reference voltage sources System level power savings Fast power-up and power-down analog blocks for duty cycling Programmable AFE sequencer to minimize workload of host controller 6 kB SRAM to preprogram AFE sequences Ultra low power potentiostat channel: 6.5 µAof current consumption when powered on and all other blocks in hibernate mode Smart sensor synchronization and data collection Cycle accurate control of sensor measurement Sequencer controlled GPIOs On-chip peripherals SPI serial input/output Wake-up timer Interrupt controller Power 2.8 V to 3.6 V supply 1.82 V input/output compliant Power-on reset Hibernate mode with low power DAC and potentiostat amplifier powered up to maintain sensor bias Package and temperature range 3.6 mm × 4.2 mm, 56-ball WLCSP 7 mm × 7 mm, 48-lead LFCSP Fully specified for operating temperature range of −40°C to +85°C AD5940 and AD5941 fully specified for operating temperature range of −40°C to +85°C AD5941W fully specified for operating temperature range of −40°C to +105°C AEC-Q100 qualified for automotive applications

High Common-Mode Voltage, Programmable Gain Difference Amplifier Features: High common-mode input voltage range ±120 V at VS = ±15 V Gain range 0.1 to 100 Operating temperature range: −40°C to +85°C Supply voltage range Dual supply: ±2.25 V to ±18 V Single supply: 4.5 V to 36 V Excellent ac and dc performance Offset temperature stability RTI: 10 μV/°C maximum Offset: ±1.5 V mV maximum CMRR RTI: 75 dB minimum, dc to 500 Hz, G = +1

250 MHz Demodulating Logarithmic Amplifier Features: Logarithmic amplifier performance Usable to 250 MHz 44 dB dynamic range ±2.0 dB log conformance 37.5 mV/dB voltage output Stable slope and intercepts 2.0 nV/√Hz input noise voltage 50 mV input offset voltage Low power ±5 V supply operation 9 mA (+VS), 35 mA (–VS) quiescent current Onboard resistors Onboard 10× attenuator Dual polarity current outputs Direct coupled differential signal path

4-Channel, I2C, Ultralow Power 12-Bit ADC in 20-Lead LFCSP/TSSOP Features: I2C-compatible serial interface supports standard and fast modes Ultralow power: 90 μW typical at 3 V in fast mode Specified for VDD of 2.7 V to 5.25 V On-chip accurate 2.5 V reference, 5 ppm/°C typical drift 4 single-ended analog input channels ALERT function BUSY function Autocycle mode Wide input bandwidth 68 dB signal-to-noise ratio (SNR) typical at input frequency of 1 kHz Flexible power/throughput rate management No pipeline delays Power-down mode 550 nA typical at VDD = 5.25 V 435 nA typical at VDD = 3 V 20-lead LFCSP and TSSOP packages Temperature range: −40°C to +125°C

4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: Three power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator On-chip bias voltage generator Low-side power switch General-purpose outputs Multiple filter options Internal temperature sensor Self and system calibration Sensor burnout detection Automatic channel sequencer Per channel configuration Power supply: 2.7 V to 3.6 V and ±1.8 V Independent interface power supply Power-down current: 5 μA maximum Temperature range: −40°C to +125°C 32-lead LFCSP/24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ESD: 4 kVAD7124-4-EP Supports defense and aerospace applications (AQEC standard) Download AD7124-4-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19614

8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: 3 power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification) Crosspoint multiplexed analog inputs 8 differential/15 pseudo differential inputs See data sheet for additional features

2.5 V to 5.5 V, 250 A, 2-Wire Interface, Dual Voltage Output,12-Bit DACs Features: AD5337: 2 buffered 8-bit DACs in 8-lead MSOP AD5338, AD5338-1: 2 buffered 10-bit DACs in 8-lead MSOP AD5339: 2 buffered 12-bit DACs in 8-lead MSOP Low power operation: 250 μA @ 3 V, 300 μA @ 5 V 2-wire (I2C-compatible) serial interface 2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes See datasheet for additional features

2.5V to 5.5V, 115A Parallel Interface Single Voltage Output 10-Bit DAC Features: Single 10-Bit DAC in 20-Lead TSSOP Low power operation: 115 μA @ 3 V, 140 μA @ 5 V Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin 2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes Double-Buffered Input Logic Buffered/unbuffered reference input options See Data Sheet for Additional Information

2.5 V to 5.5 V, 230 A, Dual Rail-to-Rail Voltage Output 12-Bit DAC Features: AD5313: 2 buffered 10-bit DACs in 1 package A version: ±4 LSB INL B version: ±2 LSB INL AD5323: 2 buffered 12-bit DACs in 1 package A version: ±16 LSB INL  B version: ±8 LSB INL 16-lead TSSOP package Power-down to 200 nA @ 5 V, 50 nA @ 3 V Micropower operation: 300 μA at 5 V (including reference current) 2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/unbuffered reference input options Output range: 0 V to VREF or 0 V to 2 VREF Power-on-reset to 0 V