400 MHz TO 4000 MHz Low Noise Amplifier Features: Operation from 400 MHz to 4000 MHz Noise figure of 0.8 dB at 900 MHz Requires few external components Integrated active bias control circuit Integrated dc blocking capacitors Adjustable bias for low power applications Single-supply operation from 3 V to 5 V Gain of 20.8 dB at 900 MHz OIP3 of 37.0 dBm at 900 MHz P1dB of 21.8 dBm at 900 MHz Small footprint LFCSP Pin-compatible version with 21.5 dB gain available

21.2 GHz to 23.6 GHz, Low Noise Amplifier Features: Frequency range: 21.2 GHz to 23.6 GHz Typical gain of >22.5 dB Low noise input Noise figure 3.3 dB typical at 21.2 GHz 3.4 dB typical at 23.6 GHz High linearity input ≥1.0 dBm typical input third-order intercept (IIP3) −8 dBm input 1 dB compression point (P1dB) at 23.6 GHz Matched 50 Ω single-ended input Matched 100 Ω differential outputs 8-lead, 2.00 mm × 2.00 mm LFCSP microwave packaging

Silicon SPDT Switch, Reflective, 35 GHz to 44 GHz Features:Reflective design Low insertion loss: 1.8 dB at 44 GHz High isolation: 28 dB at 44 GHz High input linearity 0.1 dB power compression (P0.1dB): 37 dBm Third-order intercept (IP3): 52 dBm High RF power handling: 28 dBm average 36 dBm peak Single supply operation: 3.3V Internal negative voltage generator (NVG) RF settling time (0.1 dB final RF output): 45 ns 20-terminal, 3 mm × 3 mm, land grid array package Pin compatible with the ADRF5300: 24 GHz - 32 GHz

Dual-Channel, 3.7 GHz to 5.3 GHz, Receiver Front End Features: Integrated dual-channel RF front end 2-stage LNA and high power SPDT switch On-chip bias and matching Single supply operation Gain High gain mode: 33 dB typical at 4.6 GHz Low gain mode: 18 dB typical at 4.6 GHz Low noise figure High gain mode: 1.6 dB typical at 4.6 GHz Low gain mode: 1.6 dB typical at 4.6 GHz High channel to channel isolation  Between RxOUT-ChA and RxOUT-ChB: 45 dB typical Between TERM-ChA and TERM-ChB: 53 dB typical  Low insertion loss: 0.5 dB typical at 4.6 GHz High power handling at TCASE = 105°C Full lifetime LTE average power (9 dB PAR): 40 dBm Single event (<10 sec operation) LTE average power (9 dB PAR): 43 dBm High OIP3: 31 dBm typical Power-down mode and low gain mode for LNA Low supply current High gain mode: 86 mA typical at 5 V Low gain mode: 36 mA typical at 5 V Power-down mode: 12 mA typical at 5 V Positive logic control 40-lead, 6 mm × 6 mm LFCSP 

0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz Features:Ultrawideband frequency range: 100 MHz to 40 GHz Attenuation range: 0.5 dB steps to 31.5 dB Low insertion loss with impedance match 2.1 dB up to 18 GHz 2.9 dB up to 26 GHz 4.8 dB up to 40 GHz Attenuation accuracy with impedance match ±(0.10 + 1.0% of attenuation state) up to 18 GHz ±(0.15 + 0.8% of attenuation state) up to 26 GHz ±(0.35 + 2.5% of attenuation state) up to 40 GHz Typical step error with impedance match ±0.18 dB up to 18 GHz ±0.23 dB up to 26 GHz ±0.51 dB up to 40 GHz High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 27 dBm IP3: 50 dBm typical High RF input power handling: 27 dBm average, 30 dBm peak Tight distribution in relative phase No low frequency spurious signals SPI and parallel mode control, CMOS/LVTTL compatible RF settling time (0.1 dB of final RF output): 250 ns 24-terminal, 4 mm × 4 mm LGA package Pin compatible with ADRF5720, low frequency cutoff version

Dual Narrow/Wideband RF Transceiver Features: 2 2 highly integrated transceiver Frequency range of 30 MHz to 6000 MHz Transmitter and receiver bandwidth from 12 kHz to 40 MHz Two fully integrated, fractional-N, RF synthesizers LVDS and CMOS synchronous serial data interface options Low power monitor and sleep modes Multichip synchronization capabilities Fast frequency hopping Dynamic profile switching for dynamic data rates and sample rates Fully programmable via a 4-wire SPI 12 mm 12 mm, 196-ball CSP_BGA

Integrated Dual RF Receiver Features: Dual receivers Maximum Receiver BW: 200 MHz Fully integrated, fractional-N, RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuneable range: 75 MHz to 6000 MHz

Integrated Dual RF Transmitter and Observation Receiver Features: Dual transmitters Dual input shared observation Rx Maximum tunable Tx synthesis BW: 450 MHz Maximum observation Rx BW: 450 MHz Fully integrated fractional-N RF synthesizers Fully integrated clock synthesizer Multi-chip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuning range: 75 MHz to 6000 MHz

Integrated Dual RF Tx, Rx, and Observation Rx Features: Dual transmitters Dual receivers Dual input shared observation receiver Maximum receiver bandwidth: 200 MHz Maximum tunable transmitter synthesis bandwidth: 450 MHz Maximum observation receiver bandwidth: 450 MHz Fully integrated fractional-N RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuning range (center frequency): 75 MHz to 6000 MHz

Integrated Dual RF Tx, Rx, and Observation Rx Features: Dual transmitters Dual receivers Dual input shared observation receiver Maximum receiver bandwidth: 200 MHz Maximum tunable transmitter synthesis bandwidth: 450 MHz Maximum observation receiver bandwidth: 450 MHz Fully integrated fractional-N RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuning range (center frequency): 75 MHz to 6000 MHz