Demo circuit 1069A is a monolithic step-down switching regulator with LDO featuring LT3500. The demo circuit is designed for 5.0V and 3.3V outputs from a 6V to 36V input. The LDO output is configured as a post-regulator of the switching regulator output. The total current capability is up to 2A. The switching regulator can be synchronized to an external clock input or be resistor-programmed to a 250kHz to 2.2MHz internal oscillator. Programmable frequency allows for optimization between efficiency and external component size. Cycle-by-cycle current limit, frequency foldback and thermal shutdown provide protections against a shorted output. The soft-start feature controls the ramp rate of the output voltage, eliminates input current surge during startup, and also provides output tracking.

Demonstration circuit 1072B is a step-down converter using the LTC3561A monolithic synchronous buck regulator. The DC1072B has an input voltage range of 2.5V to 5.5V, and is capable of delivering up to 1A of output current at a jumper-selectable output voltage of 1.2V, 1.5V, 1.8V or user-defined.

DC1082A-D: Demo Board for the LTC1403A Serial 14-Bit, 2.8Msps Sampling ADCs with Shutdown.

The LTC2356-12/LTC2356-14 are 12-bit/14-bit, 3.5Msps serial ADCs with differential inputs. The devices draw only 5.5mA from a single 3.3V supply and come in a tiny 10-lead MSOP package. A Sleep shutdown feature further reduces power consumption to 13?W. The combination of speed, low power and tiny package makes the LTC2356-12/LTC2356-14 suitable for high speed, portable applications.The 80dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source.The devices convert ?1.25V to 1.25V bipolar inputs differentially. The absolute voltage swing for AIN+ and AIN? extends from ground to the supply voltage.The serial interface sends out the conversion results during the 16 clock cycles following a CONV rising edge for compatibility with standard serial interfaces. If two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 3.5Msps can be achieved with a 63MHz clock. Bits LTC2356-12 12 LTC2356-14 14 Applications Communications Data Acquisition Systems Uninterrupted Power Supplies Multiphase Motor Control Multiplexed Data Acquisition RFID

Demonstration circuit 1092 is a monolithic step-down DC/DC switching converter featuring the LT1933H in the 2×3 DFN-6 package and operating over the H-grade temperature range. The board is optimized for 3.3V output at up to 500mA load current and requires an input voltage ranging from 4.5V to 36V.

DC1094A: Demo Board for LTC4095 Standalone USB Li-Ion/Polymer Battery Charger in 2mm x 2mm DFN

DC1098A-B: Demo Board for LTC2283 Dual 12-Bit, 125Msps Low Power 3V ADC

DC1101A: Demo Board for LTC4097 USB/Wall Adapter Standalone Li-Ion/Polymer Battery Charger

DC1103A: Demo Board for LTC6410-6 Low Distortion, Low Noise Differential IF Amplifier with Configurable Input Impedance

The AD9142A is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1600 MSPS, permitting a multicarrier generation up to the Nyquist frequency. The AD9142A TxDAC+? includes features optimized for direct conversion transmit applications, including complex digital modulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series and the ADRF670x series from Analog Devices, Inc. A 3-wire serial port interface provides for the programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 9 mA to 33 mA. The AD9142A is available in a 72-lead LFCSP.PRODUCT HIGHLIGHTS Wide signal bandwidth (BW) enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. Very small inherent latency variation simplifies both software and hardware design in the system. It allows easy multichip synchronization for most applications. New low power architecture improves power efficiency (mW/MHz/channel) by 30%. Input signal power and FIFO error detection simplify designs for downstream analog circuitry protection. Programmable transmit enable function allows easy design balance between power consumption and wakeup time.APPLICATIONS Wireless communications: 3G/4G and MC-GSM base stations, wideband repeaters, software defined radios Wideband communications: point-to-point, LMDS/MMDS Transmit diversity/MIMO Instrumentation Automated test equipment