Dual, Simultaneous Sampling, 14-Bit, 4 MSPS, SAR ADCs, Pseudo Differential Input Features: Dual 16-bit/14-bit ADC family Dual simultaneous sampling Pseudo differential analog inputs 4 MSPS throughput conversion rate SNR (typical) 87.5 dB, VREF = 3.3 V external for 16-bit AD7383 83.5 dB, VREF = 3.3 V external for 14-bit AD7384 93.4 dB with RES = 1 and OSR = 8 On-chip oversampling function Resolution boost function INL error (maximum) 2.5 LSBs for 16-bit AD7383 1.0 LSB for 14-bit AD7384 2.5 V internal reference High speed serial interface 40C to +125C operation 16-lead LFCSP, 3 mm 3 mm Alert function

Dual, Simultaneous Sampling, 14-Bit, 4 MSPS, SAR ADCs, Pseudo Differential Input Features: Dual 16-bit/14-bit ADC family Dual simultaneous sampling Pseudo differential analog inputs 4 MSPS throughput conversion rate SNR (typical) 87.5 dB, VREF = 3.3 V external for 16-bit AD7383 83.5 dB, VREF = 3.3 V external for 14-bit AD7384 93.4 dB with RES = 1 and OSR = 8 On-chip oversampling function Resolution boost function INL error (maximum) 2.5 LSBs for 16-bit AD7383 1.0 LSB for 14-bit AD7384 2.5 V internal reference High speed serial interface 40C to +125C operation 16-lead LFCSP, 3 mm 3 mm Alert function

+3/+5 Volt Serial-Input Micropower 12-Bit DAC Features: Micropower - 100 µA Single Supply - 2.7 V to 5.5 V Operation Compact 1.75 mm Height SO-8 Package and 1.1 mm Height TSSOP-8 Package AD7390 - 12-Bit Resolution AD7391 - 10-Bit Resolution SPI and QSPI Serial Interface Compatible with Schmitt Trigger Inputs

Linear Voltage Regulator IC Positive Fixed 1 Output 150mA 8-MSOP

HBT Vector Modulator SMT, 1.8 - 2.2 GHz Features: Continuous Phase Control: 360°  Continuous Gain: 40 dB Control Output Noise Floor: -162 dBm/Hz Input IP3: +33 dBm 3×3 mm QFN Plastic Package

Dual, 16-Bit, 2.8 GSPS, TxDAC+ Digital-to-Analog Converter Features: Support input data rate >2 GSPS Proprietary low spurious and distortion design SFDR = 82 dBc at dc IF, −9 dBFS Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Selectable 1×, 2×, 4×, or 8× interpolation filter Low power architecture Transmit enable function allows extra power saving and instant control of the output status High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Low power: 1.42 W at 1.6 GSPS full operating conditions 88-lead LFCSP with exposed pad

Quad, 16-Bit, 2.4 GSPS, TxDAC+ Digital-to-Analog Converter Features: Supports input data rates up to 1 GSPS Proprietary, low spurious and distortion design Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at 180 MHz IF Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at 180 MHz IF SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Input signal power detection High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Digital quadrature modulation using a numerically controlled oscillator (NCO) Nyquist band selection—mix mode Selectable 1×, 2×, 4×, and 8× interpolation filters Low power: 2.11 W at 1.6 GSPS, full operating conditions 88-lead, exposed pad LFCSP

DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84 GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch