Silicon SPDT Switch, Nonreflective, 100 MHz to 44 GHz Features: Ultrawideband frequency range: 100 MHz to 44 GHz Nonreflective design Low insertion loss: 1.2 dB to 18 GHz 1.7 dB to 26 GHz 2.4 dB to 40 GHz 3.8 dB to 44 GHz High isolation 55 dB to 18 GHz 53 dB to 26 GHz 50 dB to 40 GHz 45 dB to 44 GHz High input linearity P1dB: 27 dBm typical IP3: 53 dBm typical High power handling 24 dBm insertion loss path 24 dBm isolation path All off state control No low frequency spurious signals 0.1 dB RF settling time: 40 ns typical 20-terminal, 3 mm × 3 mm LGA package Pin compatible with ADRF5027, low frequency cutoff versionADRF5026-EP supports defense and aerospace applications (AQEC standard) Download ADRF5026-EP data sheet (pdf) Supports defense and aerospace applications (AQEC standard) Military temperature range (−55°C to +105°C) Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/21601 DSCC Drawing Number

Nonreflective, 9 kHz to 44 GHz Silicon SP4T Switch Features: Ultrawideband frequency range: 9 kHz to 44 GHz Nonreflective 50 Ω design Low insertion loss: 1.5 dB at 18 GHz 2.4 dB at 40 GHz 2.5 dB at 44 GHz High isolation: 44 dB at 18 GHz 39 dB at 40 GHz 36 dB at 44 GHz High input linearity: P0.1dB: 26 dBm typical IP3: 48 dBm typical High power handling 24 dBm through path 24 dBm terminated path All off state control Logic select control No low frequency spurs Settling time (0.1 dB final RF output): 6 μs 24-terminal, 3 mm × 3 mm LGA package Pin compatible with ADRF5042, fast switching version

Silicon SPDT Switch, Reflective, 35 GHz to 44 GHz Features:Reflective design Low insertion loss: 1.8 dB at 44 GHz High isolation: 28 dB at 44 GHz High input linearity 0.1 dB power compression (P0.1dB): 37 dBm Third-order intercept (IP3): 52 dBm High RF power handling: 28 dBm average 36 dBm peak Single supply operation: 3.3V Internal negative voltage generator (NVG) RF settling time (0.1 dB final RF output): 45 ns 20-terminal, 3 mm × 3 mm, land grid array package Pin compatible with the ADRF5300: 24 GHz - 32 GHz

Dual-Channel, 3.7 GHz to 5.3 GHz, Receiver Front End Features: Integrated dual-channel RF front end 2-stage LNA and high power SPDT switch On-chip bias and matching Single supply operation Gain High gain mode: 33 dB typical at 4.6 GHz Low gain mode: 18 dB typical at 4.6 GHz Low noise figure High gain mode: 1.6 dB typical at 4.6 GHz Low gain mode: 1.6 dB typical at 4.6 GHz High channel to channel isolation  Between RxOUT-ChA and RxOUT-ChB: 45 dB typical Between TERM-ChA and TERM-ChB: 53 dB typical  Low insertion loss: 0.5 dB typical at 4.6 GHz High power handling at TCASE = 105°C Full lifetime LTE average power (9 dB PAR): 40 dBm Single event (<10 sec operation) LTE average power (9 dB PAR): 43 dBm High OIP3: 31 dBm typical Power-down mode and low gain mode for LNA Low supply current High gain mode: 86 mA typical at 5 V Low gain mode: 36 mA typical at 5 V Power-down mode: 12 mA typical at 5 V Positive logic control 40-lead, 6 mm × 6 mm LFCSP 

2 dB LSB, 4-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz Features: Ultrawideband frequency range: 100 MHz to 40 GHz Attenuation range: 2 dB steps to 30 dB Low insertion loss 1.7 dB to 18 GHz 2.2 dB to 26 GHz 3.5 dB to 40 GHz Attenuation accuracy ±(0.1 + 2.0%) of attenuation state up to 18 GHz ±(0.2 + 2.5%) of attenuation state up to 26 GHz ±(0.5 + 10.0%) of attenuation state up to 40 GHz High RF input power handling: 26 dBm average, 30 dBm peak Tight distribution in relative phase Typical step error ±0.15 dB to 18 GHz ±0.20 dB to 26 GHz ±0.60 dB to 40 GHz High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 26 dBm IP3: 50 dBm typical No low frequency spurious signals SPI and parallel mode control, CMOS/LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 230 ns 2.5 mm × 2.5 mm, 16-terminal LGA package Pin compatible with ADRF5721, low frequency cutoff version

Quad,12-Bit nanoDAC with 5ppm/C On-Chip Reference Features: Low power, smallest pin-compatible, quad nanoDACs  AD5664R: 16 bits AD5644R: 14 bits AD5624R: 12 bits User selectable external or internal reference External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference 10-lead MSOP; 10-lead, 3 mm × 3 mm LFCSP_WD; and 12-ball, 1.665 mm × 2.245 mm WLCSP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Serial interface, up to 50 MHz

Dual, 12-Bit nanoDAC with I2C Interface Features: AD5627R/AD5647R/AD5667R 12-/14-/16-bit On-chip 1.25 V/2.5 V, 5 ppm/°C reference AD5627/AD5667 12-/16-bit External reference only 3 mm x 3 mm LFCSP and 10-lead MSOP 2.7 V to 5.5 V power supply Low power, smallest pin-compatible, dual nanoDACs Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Hardware LDAC and CLR functions I2C-compatible serial interface supports standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes

12-bit Digital-to-Analog Converters, with Zener Reference Features: Single Chip Construction Very High Speed Settling to 1/2 LSB AD565A: 250 ns max Full-Scale Switching Time: 30 ns Guaranteed for Operation with ±12 V (AD565A) Supplies Low Cost Linearity Guaranteed Over temperature 1/2 LSB max (K, T Grades) Monotonicity Guaranteed Over temperature Low Power = 225mW max Use with On-Board High Stability Reference

Quad, 16-Bit nanoDAC with 5ppm/C On-Chip Reference Features: Low power, smallest pin-compatible, quad nanoDACs  AD5664R: 16 bits AD5644R: 14 bits AD5624R: 12 bits User selectable external or internal reference External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference 10-lead MSOP; 10-lead, 3 mm × 3 mm LFCSP_WD; and 12-ball, 1.665 mm × 2.245 mm WLCSP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Serial interface, up to 50 MHz

Octal, 16-Bit nanoDAC+ with 2 ppm/C Reference, I2CInterface Features: High Performance High relative accuracy (INL): ±3 LSB maximum at 16 bits Total unadjusted error (TUE): ±0.14% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.06% of FSR maximum Low drift 2.5 V reference: 2 ppm/°C typical Wide Operating Ranges −40°C to +125°C temperature range 2.7 V to 5.5 V power supply Easy Implementation User selectable gain of 1 or 2 (GAIN pin/bit) 1.8 V logic compatibility 400 kHz I2C-compatible serial interface 20-lead, RoHS-compliant TSSOP and LFCSP