The fourth generation of SHARC® Processors now includes the low power floating point DSP products – the ADSP-21478 and ADSP-21479 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting a single chip solution. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats and their low power make them particularly suitable for battery powered applications or where a higher ambient operating temperature is required.The ADSP-21478 offers a very low power and high performance – 266 MHz/1596 MFLOPs – in a BGA and LQFP package within the fourth generation SHARC Processor family. This feature of power makes the ADSP-21478 particularly well suited to address the automotive audio and many industrial control segments where low power is a requirement. In addition to its high core performance, the ADSP-21478 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The SHARC ADSP-21489 is one of two new members of the fourth generation of SHARC® Processors that now includes the ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.The ADSP-21489 offers the highest performance–450 MHz/2700 MFLOPs–in an LQFP package within the fourth generation SHARC Processor family. This level of performance makes the ADSP-21489 particularly well suited to address the automotive audio and industrial control segments. In addition to its high core performance, the ADSP-21489 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, IDP, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as SPI,UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The BF592 is the low cost entry point into the Blackfin portfolio of processors. With core clock speeds of 200 and 400 MHz and a peripheral set including two SPORT’s, a PPI, two SPI’s, four general purpose counters and a factory-programmed Instruction ROM block containing the VDK RTOS and C-runtime libraries, the BF592 is feature and cost optimized for compute intensive industrial, automotive, and general purpose applications that do not require external memory or executable flash. The BF592 is offered in a low cost 9×9mm LFCSP package in commercial and industrial temperature grades as well as automotive qualified. 

BLACKFIN DIGITAL SIGNAL PROCESSORS;

The dual-core ADSP-BF606 Blackfin processor is optimized for a broad range of industrial, instrumentation, medical, and consumer applications demanding complex control and signal processing tasks while maintaining extremely high data throughput.Features include a high performance enhanced infrastructure, large on-chip memory and a feature rich peripheral set with expanded connectivity options including USB 2.0 HS OTG, 2 10/100 Ethernet MACs, and Removable Storage Interface (RSI).In addition to these the ADSP-BF606 processor contains features for safety-critical applications, including a CRC for memory protection, Parity and ECC protection in the internal memory blocks and a Fault Management Unit.

This device is a member of the ADSP-BF70x Blackfin Digital Signal Processor (DSP) product family. The new Blackfin+ processor core combines dual-MAC 16-bit, 32-bit MAC and 16-bit complex MAC in to a state-of-the-art signal processing engine. It also combines advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities within a single instruction-set architecture. Further new enhancements to the Blackfin+ core add cache enhancements, branch prediction and other instruction set improvements—all while maintaining instruction set compatibility to previous Blackfin products.The processor offers performance up to 400 MHz, as well as lowest power consumption at <100mW. Produced with a low-power and low-voltage design methodology, they provide world-class power management and performance.By integrating a rich set of industry-leading system peripherals and large on-chip memory, this Blackfin processor is the platform of choice for next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package. These applications span a wide array of markets, from automotive systems to embedded industrial, instrumentation, video/image analysis, biometric and control applications.

This device is a member of the ADSP-BF70x Blackfin Digital Signal Processor (DSP) product family. The new Blackfin+ processor core combines dual-MAC 16-bit, 32-bit MAC and 16-bit complex MAC in to a state-of-the-art signal processing engine. It also combines advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities within a single instruction-set architecture. Further new enhancements to the Blackfin+ core add cache enhancements, branch prediction and other instruction set improvements—all while maintaining instruction set compatibility to previous Blackfin products.The processor offers performance up to 400 MHz, as well as lowest power consumption at By integrating a rich set of industry-leading system peripherals, large on-chip memory & a high speed external memory interface, this Blackfin processor is the platform of choice for next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package. These applications span a wide array of markets, from automotive systems to embedded industrial, instrumentation, video/image analysis, biometric and control applications.

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC® family of products. The ADSP-SC57x processor is based on the SHARC+® dual-core and the arm® Cortex®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.By integrating a set of industry leading system peripherals and memory, the arm® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

Dual-core SHARC+ and Arm Cortex-A5 SOC, DDR, Ethernet, USB, 349-cspBGA Features:SHARC+ Core Infrastructure: 500 MHz (3.0 GFLOPS) per core 5Mbits/640KB L1 memory/core with parity Optional cache/SRAM mode 32-bit, 40-bit & 64-bit floating point supportARM Core Infrastructure: 450 MHz ARM Cortex-A5 (with Neon/FPU) 32kByte/32kByte L1 Instr./Data Cache 256kByte L2 CacheShared System Memory: 256KB L2 SRAM with ECC protectionUp to Two High Speed Memory Controllers: DDR3-900, DDR2-800 & LPDDR (16-bit)Advanced Hardware Accelerators: FFT/iFFT (20 GFLOPS, 5usec per 1K-pt FFT) FIR/IIR and SINC Filters, ASRC Security Crypto Engines with OTPPackaging: 19mm x 19mm BGA (0.8mm pitch) Commercial, Industrial & AutomotivePeripherals: Gigabit Ethernet MAC (RGMII) With IEEE-1588 & AVB support (QoS & clock recovery) USB2.0 HS OTG/Device Controllers (MAC/PHY) 2x CAN2.0 MLB 3/6-pin (Auto devices only) Up to 8x Full SPORT interfaces (w/ TDM & I2S modes) S/PDIF Tx/Rx, 8x ASRC pairs, PCG 2x Dual-SPI and 1x QuadSPI (w/ direct execution) 3x I2C and 3x UARTs (w/ Flow Control) Enhanced Parallel Peripheral Interface For video I/O or parallel converter interface 2x Link Ports (bi-directional, 8-bit, up to 150MB/sec) 3x Enhanced PWM, ADC Control Module (ACM) 8x GP Timer, 1x GP Counter, WDT and RTC Up to 80 GPIO (mux’ed w/ other interfaces) 8-ch 12-bit 1MSPS Housekeeping ADC Thermal Sensor

Dual-core SHARC+ and Arm Cortex-A5 SOC, DDR, Ethernet, USB, 349-cspBGA Features:SHARC+ Core Infrastructure: 500 MHz (3.0 GFLOPS) per core 5Mbits/640KB L1 memory/core with parity Optional cache/SRAM mode 32-bit, 40-bit & 64-bit floating point supportARM Core Infrastructure: 450 MHz ARM Cortex-A5 (with Neon/FPU) 32kByte/32kByte L1 Instr./Data Cache 256kByte L2 CacheShared System Memory: 256KB L2 SRAM with ECC protectionUp to Two High Speed Memory Controllers: DDR3-900, DDR2-800 & LPDDR (16-bit)Advanced Hardware Accelerators: FFT/iFFT (20 GFLOPS, 5usec per 1K-pt FFT) FIR/IIR and SINC Filters, ASRC Security Crypto Engines with OTPPackaging: 19mm x 19mm BGA (0.8mm pitch) Commercial, Industrial & AutomotivePeripherals: Gigabit Ethernet MAC (RGMII) With IEEE-1588 & AVB support (QoS & clock recovery) USB2.0 HS OTG/Device Controllers (MAC/PHY) 2x CAN2.0 MLB 3/6-pin (Auto devices only) Up to 8x Full SPORT interfaces (w/ TDM & I2S modes) S/PDIF Tx/Rx, 8x ASRC pairs, PCG 2x Dual-SPI and 1x QuadSPI (w/ direct execution) 3x I2C and 3x UARTs (w/ Flow Control) Enhanced Parallel Peripheral Interface For video I/O or parallel converter interface 2x Link Ports (bi-directional, 8-bit, up to 150MB/sec) 3x Enhanced PWM, ADC Control Module (ACM) 8x GP Timer, 1x GP Counter, WDT and RTC Up to 80 GPIO (mux’ed w/ other interfaces) 8-ch 12-bit 1MSPS Housekeeping ADC Thermal Sensor