Single-core SHARC+ (w/384KB L1), arm Cortex-A5, 1MB Shared L2, 10/100 Ethernet, 176-LQFP Features: Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed arm® Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity 256 kB L2 cache with parity Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature rangeMemory Large on-chip L2 SRAM with ECC protection, up to 1 MB One L3 interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devicesAdditional Features Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for arm® TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications

BLACKFIN EMBEDDED Processor

Blackfin Embedded Symmetric Multiprocessor

BLACKFIN EMBEDDED Processor

High Performance Convergent Multimedia Blackfin Processor Features: Lockbox™ Secure Technology: Hardware-enabled security for code and content protection Multimedia: Multiple Enhanced Parallel Peripheral Interfaces (EPPI), Pixel Compositor hardware accelerator Human Interface: 18/24-bit LCD Controller 32-bit Up/Down counter/Thumbwheel interface, 8x8 Keypad interface Blackfin® Processor Core with up to 600Mhz (1200 MMACS) Performance Two independent DMA controllers Connectivity: High Speed USB OTG , Host DMA, UARTs, SPORTs, SPI, and TWI Expansion: SD/SDIO and ATAPI-6 Controllers Synchronous interface for DDR or Mobile DDR connectivity (See data sheet ordering guide for specific product information) Asynchronous memory interface for SRAM, EEPROM, NAND/NOR, Flash connectivity

400MHz SHARC+ DSP with 640KB L1, 256KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 400 (max) Core clock frequency 640KB Level 1 (L1) SRAM memory with parity (optional ability to configure cache) 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 256KB on-chip Level 2 (L2) SRAM with ECC protection, up to 8 Mb (1 MB)Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EPAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Up to 800MHz SHARC+ DSP with 640KB L1, 512KB Shared L2 SRAM, 400-Ball CSP_BGA Features:SHARC+ Core infrastructure 600MHz (max) or 800MHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 512KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 10x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 4-ch 12bit Housekeeping ADCs 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

800 MHz Dual-SHARC+ DSP with 2x 640KB L1, 1024KB Shared L2 SRAM, 400-Ball FCBGA Features:SHARC+ Core Infrastructure 800 MHz (max) Core clock frequency 2x 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024 KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices)16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 8x Precision Clock Generators 2x 4-channel PDM Mic Inputs 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 16x General Purpose Timer, 1x General Purpose Counter 3x Watchdog Timers 4-ch 12bit Housekeeping ADC 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball FCBGA Fully pin-compatible with ADSP-21569, ADSP-21567, and ADSP-21566 processorsAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Low Power 400MHz Blackfin+ Embedded Processor with 512KByte L2 SRAM & DDR2/LPDDR Interface Features: Blackfin+ core with up to 400 MHz performance Dual 16-bit or single 32-bit MAC support per cycle 16-bit complex MAC and many other instruction set enhancements Instruction set compatible with previous Blackfin products On-Chip Memory 136KB L1 SRAM with multi-parity-bit protection (64KB instruction, 64KB data, 8KB scratchpad) 512KByte on-chip L2 SRAM with ECC protection L3 interface providing 16-bit interface to DDR2 or LPDDR SDRAM devices (up to 200 MHz) Key Peripherals include USB2.0 HS OTG 2x CAN2.0B ePPI Video I/O 2x SPORTs (w/I2S) 2xQuad-SPI / 1xDual-SPI (w/ Host mode option) I2C 2xUART SD/SDIO/MMC (8-bit) 4-ch 12-bit 1MSPS ADC Security and one-time-programmable memory Crypto hardware accelerators for fast secure boot/IP protection memDMA encryption/decryption for fast run-time security Low-cost packaging 184-Ball CSP_BGA package (12 mm × 12mm × 0.8mm pitch), RoHS compliant Low system power with < 100 mW at 400 MHz (< 0.25 mW/MHz) at 25°C TJUNCTION

Low Power 400MHz Blackfin+ Embedded Processor with 1MByte L2 SRAM Features: Blackfin+ core with up to 400 MHz performance Dual 16-bit or single 32-bit MAC support per cycle 16-bit complex MAC and many other instruction set enhancements Instruction set compatible with previous Blackfin products On-Chip Memory 136KB L1 SRAM with multi-parity-bit protection (64KB instruction, 64KB data, 8KB scratchpad) 1MByte on-chip L2 SRAM with ECC protection 512KByte On-chip L2 ROM Key Peripherals include USB2.0 HS OTG 2x CAN2.0B ePPI Video I/O 2x SPORTs (w/I2S) 2xQuad-SPI / 1xDual-SPI (w/ Host mode option) I2C 2xUART SD/SDIO/MMC (4-bit) Security and one-time-programmable memory Crypto hardware accelerators for fast secure boot/IP protection memDMA encryption/decryption for fast run-time security Low-cost packaging 88-Lead LFCSP (QFN) package (12 mm × 12mm), RoHS compliant Low system power with < 100 mW at 400 MHz (< 0.25 mW/MHz) at 25°C TJUNCTION