The EV-21569-SOM with low-cost evaluation and rapid prototyping of the ADSP-2156× Family (ADSP-21562/21563/21565/21566/21567/21569) of SHARC+ audio processors. It features the processor, memory, and power portions of the design and provides an easy-to-use plug-n-play reference design with all the key interfaces made available on three connectors for marrying to either the EV-SOMCRR-EZKIT carrier board or a custom carrier board. The EV-21569-SOM and EV-SOMCRR-EZKIT boards may be purchased as a bundle (EV-21569-EZKIT), providing fast and easy evaluation of the processor core and system peripherals/interfaces. The EV-21569-SOM module requires the CrossCore® Embedded Studio (CCES) development tools to enable developers to achieve faster time to market. The development environment aids advanced application code development and debug, such as: Create, compile, assemble, and link application programs written in C++, C, and assembly Load, run, step, halt, and set breakpoints in application programs Read and write data and program memory Read and write core and peripheral registers When used without the EV-SOMCRR-EZKIT carrier board, the EV-21569-SOM board requires an external in-circuit emulator (ICE-1000 or ICE-2000) be connected to the JTAG header.

DC1947A: Demo Board for the LT3799-1 Offline Isolated Flyback LED Controller with Active PFC.

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

The LTC3726 is a secondary-side controller for synchronous forward converters. When used in conjunction with the LTC3705/LTC3725 gate driver and primary-side controllers, the part creates a complete isolated power supply that combines the simplicity of OPTI-LOOP? compensation with the speed of secondary-side control.The LTC3726 has been designed to simplify the design of highly efficient, secondary-side forward converters. Working in concert with the LTC3705 or LTC 3725, the LTC3726 forms a robust, self-starting converter that eliminates the need for the separate bias regulator that is commonly used in secondary-side control applications. In addition, a proprietary scheme is used to multiplex gate drive signals and DC bias power across the isolation barrier through a single, tiny pulse transformer.The LTC3726 is available in a 16-lead SSOP package.Applications Isolated 48V Telecommunication Systems Internet Servers and Routers Distributed Power Step-Down Converters Automotive and Heavy Equipment

DAC39J82 Dual-Channel; 16-Bit; 2.8-GSPS; 1x-16x Interpolating Digital-to-Analog Converter EVM

Evaluation Board for the LM3253

Simple Switcher® Power Module 5.5Vin; 4A Demonstration Board

SN65LVP19 Evaluation Module

DC1488A-A: Demo Board for the LTC2634-12 Quad 12-Rail-to-Rail DACs with 10ppm/°C Reference.

The HMC958LC5 is a 4:1 Selector designed to support data transmission rates of up to 14 Gbps and selector port operation up to 14 GHz. The selector routes the differential inputs to either one or both of the desired outputs upon assertion of the appropriately selected port. The HMC958LC5 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All single-ended input signals to the HMC958LC5 are terminated with 50 ??to ground on-chip, and may be either AC or DC coupled. The outputs of the HMC958LC5 may be operated either differentially or single ended. Outputs can be connected directly to a 50 ??terminated system, while DC blocking capacitors may be used if the terminating system is 50 ? to a non-ground DC voltage. The HMC958LC5 operates from a single -3.3V DC supply and is available in a ceramic RoHS compliant 5 ? 5 mm SMT package.APPLICATIONS SONET OC-192 and 10 GbE 16G Fiber Channel 4:1 Multiplexer Built-In Test Broadband Test & Measurement