The ADAR2001 is a transmitter IC optimized for millimeter wave body scanning applications. Accepting a single-ended continuous wave (CW) input signal between 2.5 GHz and 10 GHz, the ADAR2001 provides gain, 4? frequency multiplication, harmonic filtering, 1:4 signal splitting, and four independently controllable power amplifiers (PAs) with differential outputs designed to directly drive dipole antennas with differential inputs.All device functions and configuration options can be accessed by a 3-wire or 4-wire Analog Devices, Inc., serial peripheral interface (SPI).Two state machines are also integrated into the ADAR2001, which facilitate easy configuration, control, and fast switching of the frequency multiplier, filter, and transmitter sections. These sequencers are programmed through the SPI and are then operated by pulsed inputs (reset and advance).The output power and chip temperature can be monitored by four on-chip detectors and a temperature sensor whose outputs are multiplexed to an 8-bit ADC. The ADAR2001 requires only a single 2.5 V supply with power consumption of 450 mW with one channel turned on.The ADAR2001 is available in a compact, 40-terminal, 6 mm ? 6 mm LGA package and is specified from ?40?C to +85?C.APPLICATIONS Millimeter Wave Imaging Security Medical Industrial Wideband local oscillator (LO) multiplier/distributor

The ADAR2004 is a 4-channel receiver IC that is optimized for millimeter wave body scanning applications. Accepting differential input signals from 10 GHz to 40 GHz, the ADAR2004 provides a low intermediate frequency (IF) output up to 800 MHz. Each receive channel also has independent gain control.The mixer local oscillator (LO) path includes a 4? multiplier requiring an applied LO frequency between 2.4 GHz and 10.1 GHz. The 4? multiplier block includes a programmable filter that helps keep harmonics down before reaching the mixer.Two programmable state machines are included to facilitate simple configuration, control, and fast switching of the frequency multiplier, filter, and receiver sections. These sequencers are programmed through the serial peripheral interface (SPI) and are then operated by pulsed inputs (reset and advance).The ADAR2004 requires only a single 2.5 V supply with power consumption of 910 mW with all channels turned on.The ADAR2004 is available in a 7 ? 7 mm, 48-terminal LGA package and is specified from ?40?C to +85?C.APPLICATIONS Millimeter wave imaging Security Medical Industrial Multichannel receivers

The ADCLK846 is a 1.2 GHz/250 MHz, LVDS/CMOS, fanout buffer optimized for low jitter and low power operation. Possible configurations range from 6 LVDS to 12 CMOS outputs, including combinations of LVDS and CMOS outputs. Two control lines are used to determine whether fixed blocks of outputs are LVDS or CMOS outputs.The clock input accepts various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS.Table 8 provides interface options for each type of connection. The SLEEP pin enables a sleep mode to power down the device.This device is available in a 24-pin LFCSP package. It is specified for operation over the standard industrial temperature range of ?40?C to +85?C.APPLICATIONS Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation

The ADCLK905 (one input, one output), ADCLK907 (dual oneinput, one output), and ADCLK925 (one input, two outputs) areultrafast clock/data buffers fabricated on the Analog Devices, Inc.,proprietary XFCB3 silicon germanium (SiGe) bipolar process.The ADCLK905/ADCLK907/ADCLK925 feature full-swing emitter coupled logic (ECL) output drivers. For PECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For NECL (negative ECL) operation, bias VCC to ground and VEE to the negative supply.The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate, 10 Gbps data rate, and 60 fs random jitter (RJ).The inputs have center tapped, 100 ?, on-chip termination resistors. A VREF pin is available for biasing ac-coupled inputs.The ECL output stages are designed to directly drive 800 mV each side into 50 ? terminated to VCC ? 2 V for a total differential output swing of 1.6 V.The ADCLK905/ADCLK907/ADCLK925 are available in 16-lead LFCSP packages.Applications Clock and data signal restoration and level shifting Automated test equipment (ATE) High speed instrumentation High speed line receivers Threshold detection Converter clocking

The ADCLK944 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.The device has a differential input equipped with center-tapped, differential, 100 ? on-chip termination resistors. The input can accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs.The ADCLK944 features four full-swing emitter-coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply.The ECL output stages are designed to directly drive 800 mV each side into 50 ? terminated to VCC ? 2 V for a total differential output swing of 1.6 V.The ADCLK944 is available in a 16-lead LFCSP and is specified for operation over the standard industrial temperature range of ?40?C to +85?C.?APPLICATIONS Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation

DC1317A-D: Demo Board for LT1952 Single Switch Synchronous Forward Controller.

DC1335B-B: Demo Board for the LTC4269-1 - IEEE 802.3at PD with Synchronous No-Opto Flyback Controller

The LTC2302/LTC2306 are low noise, 500ksps, 1-/2-channel, 12-bit ADCs with an SPI/MICROWIRE compatible serial interface. These ADCs include a fully differential sample-and-hold circuit to reduce common mode noise. The internal conversion clock allows the external serial output data clock (SCK) to operate at any frequency up to 40MHz. The LTC2302/LTC2306 operate from a single 5V supply and draw just 2.8mA at a sample rate of 500ksps. The auto-shutdown feature reduces the supply current to 14?A at a sample rate of 1ksps. The LTC2302/LTC2306 are packaged in a tiny 10-pin 3mm x 3mm DFN. The low power consumption and small size make the LTC2302/LTC2306 ideal for battery-operated and portable applications, while the 4-wire SPI compatible serial interface makes these ADCs a good match for isolated or remote data acquisition systems.Applications High Speed Data Acquisition Industrial Process Control Motor Control Accelerometer Measurements Battery-Operated Instruments Isolated and/or Remote Data Acquisition

The LTC2226H is a 12-bit 25Msps, low power 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2226H is perfect for demanding imaging and communications applications with AC performance that includes 71.4dB SNR and 90dB SFDR. DC specs include ?0.3LSB INL (typ), ?0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.25LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.Applications Automotive Industrial Wireless and Wired Broadband Communication

The LTC4221 is a 2-channel Hot Swap? controller that allows a board to be safely inserted and removed from a live backplane. Using two independent high side gate drivers to control two external N-channel pass transistors, the output voltages can be ramped up with current foldback to limit the inrush current during the start-up period. No external compensation capacitors are required at the GATE pins. The two channels can be configured to ramp up and down separately or simultaneously for supply voltages ranging from 2.7V to 13.5V and 1V to 13.5V for channels 1 and 2 respectively.Each channel has two current limit comparators that provide dual level and dual speed overcurrent circuit breaker protection after the start-up period. If any current sense voltage exceeds 100mV for 1?s or 25mV for the timeout delay (set by the CFILTER at the FILTER pin), then the FAULT latch is set and both GATE pins are pulled low.The FB pins monitor the respective channel output voltages and provide the inputs for the PWRGD comparators as well as overvoltage protection.Applications Electronic Circuit Breaker Power Supply Sequencing Live Board Insertion and Removal Industrial High Side Switch/Circuit Breaker