The ADAU1761 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback at 14 mW from a 1.8 V analog supply. The stereo audio ADCs and DACs support sample rates from 8 kHz to 96 kHz as well as a digital volume control.The SigmaDSP? core features 28-bit processing (56-bit double precision). The processor allows system designers to compensate for the real-world limitations of microphones, speakers, amplifiers, and listening environments, resulting in a dramatic improvement in the perceived audio quality through equalization, multiband compression, limiting, and third-party branded algorithms.The SigmaStudio? graphical development tool is used to program the ADAU1761. This software includes audio processing blocks such as filters, dynamics processors, mixers, and low level DSP functions for fast development of custom signal flows.The record path includes an integrated microphone bias circuit and six inputs. The inputs can be mixed and muxed before the ADC, or they can be configured to bypass the ADC. The ADAU1761 includes a stereo digital microphone input.The ADAU1761 includes five high power output drivers (two differential and three single-ended), supporting stereo head-phones, an earpiece, or other output transducer. AC-coupled or capless configurations are supported. Individual fine level controls are supported on all analog outputs. The output mixer stage allows for flexible routing of audio.APPLICATIONS Smartphones/multimedia phones Digital still cameras/digital video cameras Portable media players/portable audio players Phone accessories products

DC1488A-C: Demo Board for the LTC2634-12 Quad 12-Rail-to-Rail DACs with 10ppm/°C Reference.

The LTC2157-12/LTC2156-12/LTC2155-12 are a family of dual 250Msps/210Msps/170Msps 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 68.5dB SNR and 90dB spurious free dynamic range (SFDR). The 1.25GHz input bandwidth allows the ADC to achieve high undersampling ratio with very low attenuation. The latency is only five clock cycles.DC specs include ?0.26LSB INL (typ), ?0.16LSB DNL (typ) and no missing codes over temperature. The transition noise is 0.54LSBRMS.The digital outputs are double data rate (DDR) LVDS.The ENC+ and ENC? inputs can be driven differentially with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. Bits LTC2156-12 12 LTC2156-14 14 Applications Communications Cellular Basestations Software Defined Radios Medical Imaging High Definition Video Testing and Measurement Instruments

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

DC391A-A: Demo Board for LTC5505 RF Power Detector with Buffered Output and >40dB Dynamic Range.

The LTC2757 is an 18-bit multiplying parallel-input, current-output digital-to-analog converter that provides full 18-bit performance?INL and DNL of ?1LSB maximum?over temperature without any adjustments. 18-bit monotonicity is guaranteed in all performance grades. This SoftSpan? DAC operates from a single 3V to 5V supply and offers six output ranges (up to ?10V) that can be programmed through the parallel interface or pin-strapped for operation in a single range. In addition to its precision DC specifications, the LTC2757 also offers excellent AC specifications, including 2.1?s full-scale settling to 1LSB and 1.4nV?s glitch impulse. The LTC2757 uses a bidirectional input/output parallel interface that allows readback of any on-chip register, including DAC output-range settings; and a CLR pin and power-on reset circuit that each reset the DAC output to 0V regardless of output range.Applications Instrumentation Medical Devices Automatic Test Equipment Process Control and Industrial Automation

The ADF7012 is a low power FSK/GFSK/OOK/GOOK/ASK UHF transmitter designed for short-range devices (SRDs). The output power, output channels, deviation frequency, and modulation type are programmable by using four, 32-bit registers.The fractional-N PLL and VCO with external inductor enable the user to select any frequency in the 75 MHz to 1 GHz band. The fast lock times of the fractional-N PLL make the ADF7012 suitable in fast frequency hopping systems. The fine frequency deviations available and PLL phase noise performance facilitates narrow-band operation.There are five selectable modulation schemes: binary frequency shift keying (FSK), Gaussian frequency shift keying (GFSK), binary on-off keying (OOK), Gaussian on-off keying (GOOK), and amplitude shift keying (ASK). In the compensation register, the output can be moved in <1 ppm steps so that indirect compensation for frequency error in the crystal reference can be made.A simple 3-wire interface controls the registers. In power-down, the part has a typical quiescent current of <0.1 ?A.APPLICATIONS Low cost wireless data transfer Security systems RF remote controls Wireless metering Secure keyless entry

The LTC6430-15 is a differential gain block amplifier designed to drive high resolution, high speed ADCs with excellent linearity beyond 1000MHz and with low associated output noise. The LTC6430-15 operates from a single 5V power supply and consumes only 800mW.In its differential configuration, the LTC6430-15 can directly drive the differential inputs of an ADC. Using 1:2 baluns, the device makes an excellent 50? wideband balanced amplifier. While using 1:1.33 baluns, the device makes a high fidelity 50MHz to 1000MHz 75? CATV amplifier.The LTC6430-15 is designed for ease of use, requiring a minimum of support components. The device is internally matched to 100? differential source/load impedance. On-chip bias and temperature compensation ensure consistent performance over environmental changes.The LTC6430-15 uses a high performance SiGe BiCMOS process for excellent repeatability compared with similar GaAs amplifiers. All A-grade LTC6430-15 devices are tested and guaranteed for OIP3 at 240MHz. The LTC6430-15 is housed in a 4mm ? 4mm, 24-lead, QFN package with an exposed pad for thermal management and low inductance. For a single-ended 50? IF gain block with similar performance, see the related LTC6431-15.Applications Differential ADC Driver Differential IF Amplifier OFDM Signal Chain Amplifier 50? Balanced IF Amplifier 75? CATV Amplifier 700MHz to 800MHz LTE Amplifier

The AD9988 is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores, and four 12-bit, 4 GSPS rate, RF analog-to-digital converter (ADC) cores. The device supports four transmitter channels and four receiver channels with a 4T4R configuration. This product is well suited for four-antenna TDD transmitter applications, where the receiver path can be shared between receiver and observation modes. The GPIO pins can be configured and toggled to support different user modes, while phase coherency is maintained. The maximum radio channel bandwidth supported is 1.2 GHz in a 4T4R configuration and a sample resolution of 16 bits. The AD9988 features a 16-lane 24.75 Gbps JESD204C or 15.5 Gbps JESD204B serial data port that allows up to eight lanes per transmit/receive link, an on-chip clock multiplier, and digital signal processing capability targeted at multiband direct to RF radio applications.APPLICATIONSWireless communications infrastructureW-CDMA, LTE, LTE-A, massive multiple input multiple output (MIMO)Point to point microwave, E-band, and 5G mmWaveBroadband communications systemsDOCSIS 3.0+ cable modem termination system (CMTS)Communication test and measurement systems

The LTC4063 is a standalone linear charger for single cell lithium-ion batteries with an adjustable low dropout linear regulator (LDO). The adjustable LDO regulates an output voltage between 1.2V to 4.2V at up to 100mA load current. When the input supply (wall adapter or USB supply) is removed, the LDO regulates the output voltage without interruption. The battery charger and LDO regulator can be enabled individually.No external sense resistor or external blocking diode is required for charging due to the internal MOSFET architecture. Internal thermal feedback regulates the charge current to maintain a constant die temperature during high power operation or high ambient temperature conditions. The float voltage is fixed at 4.2V and the charge current is programmed with an external resistor. Charge termination methods include minimum charge current or maximum time. With power applied, the LTC4063 can be put into shutdown mode to reduce the supply current to 35?A and the battery drain current to less than 2?A.Other features include smart recharge, undervoltage lockout, LDO current limiting and a charge status pin to indicate when the charge cycle has completed.Applications Handheld Computers Portable MP3 Players Digital Cameras