The HMC698LP5(E) is a frequency synthesizer with a wideband reversible polarity digital PFD and lock detect output. The divider operates unconditionally from 80 - 7000 MHz with a continuous integer division ratio of 12 to 259. The HMC698LP5(E) high frequency operation along with ultra low phase noise floor make possible synthesizers with wide loop bandwidth and low N resulting in fast settling and very low phase noise. When used in conjunction with a differential loop filter, the HMC698LP5(E) can be used to phase lock a VCO to a reference oscillator.Applications Satellite Communication Systems Point-to-Point Radios Military Applications Sonet Clock Generation

The HMC736 is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC VCO. The HMC736 integrates a resonator, negative resistance device, varactor diode and feature half frequency output. The VCO's phase noise performance is excellent over temperature, shock, and process due to the oscillator's monolithic structure. Power output is +9 dBm typical from a +4.2V supply voltage. The voltage controlled oscillator is packaged in a leadless QFN 4?4 mm surface mount package, and requires no external matching components.APPLICATIONS Point-to-Multi-Point Radios Test Equipment & Industrial Controls SATCOM Military End-Use

The HMC778LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an integrated Voltage Controlled Oscillator (VCO). The input reference frequency range is DC to 350 MHz while the advanced delta-sigma modulator design in the fractional synthesizer allows both ultra-fine step sizes and very low spurious products. The highly integrated structure provides excellent phase noise performance over temperature, shock and process. In addition, the HMC778LP6CE offers frequency sweep and modulation features, external triggering, double-buffering, exact frequency control, phase modulation and more. The HMC778LP6CE is packaged in a leadless QFN 6 x 6 mm surface mount package.For theory of operation and register map refer to the 'PLLs w/ Integrated VCO - Microwave VCOs' Operating Guide.Applications VSAT Radio Microwave Point-To-Point Radios Test Equipment & Industrial Control Military End-Use Phased Array Applications FMCW Radar Systems

The ADF5000 prescaler is a low noise, low power, fixed RF divider block that can be used to divide down frequencies as high as 18 GHz to a lower frequency suitable for input to a PLL IC, such as the?ADF4156 or the ADF4106. The ADF5000 provides a divide-by-2 function. The ADF5000 operates from a 3.3 V supply and has differential 100 ? RF outputs to allow direct interface to the differential RF inputs of PLLs such as the ADF4156 and ADF4106.Applications PLL frequency range extender Point-to-point radios VSAT radios Communications test equipment?

The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for ?40?C to +85?C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front end, loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2812 is available in a compact 5 mm ? 5 mm 32-lead lead frame chip scale package (LFCSP).ApplicationsSONET OC-1/OC-3/OC-12/OC-48 and all associated FEC rates Fibre Channel, 2? Fibre Channel, GbE, HDTV WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers

The ADN2816 provides the receiver functions of quantization and clock and data recovery for continuous data rates from 10 Mb/s to 675 Mb/s. The ADN2816 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for ?40?C to +85?C ambient temperature, unless otherwise noted.The ADN2816 is available in a compact 5 mm ? 5 mm 32-lead chip scale package.ApplicationsSONET OC-1/3/12 and all associated FEC rates Fibre Channel, ESCON, Fast Ethernet, SDI, etc. WDM transpondersRegenerators/repeatersTest equipmentBroadband cross-connects and routers

The AD9516-2?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz to 2.33 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9516-2 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements. The AD9516-2 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9516-0 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9516-2 is specified for operation over the standard industrial range of ?40?C to +85?C.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

The AD9516-5?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO/VCXO of up to 2.4 GHz.The AD9516-5 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit otherapplications with demanding phase noise and jitter requirements.The AD9516-5 features six LVPECL outputs (in three pairs)and four LVDS outputs (in two pairs). Each LVDS output canbe reconfigured as two CMOS outputs. The LVPECL outputsoperate to 1.6 GHz, the LVDS outputs operate to 800 MHz, andthe CMOS outputs operate to 250 MHz.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division forthe LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allowa range of divisions up to a maximum of 1024.The AD9516-5 is available in a 64-lead LFCSP and can beoperated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. A separate LVPECL power supply can be from 2.375 V to 3.6 V (nominal).The AD9516-5 is specified for operation over the industrial range of ?40?C to +85?C.For applications requiring an integrated EEPROM, or needing additional outputs, the AD9520-5?and AD9522-5?are available.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

The AD9517-4?provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.45 GHz to 1.80 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9517-4 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9517-4 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9517-4 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9517-4 is specified for operation over the industrial range of ?40?C to +85?C.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation

The AD9520-2 provides a multioutput clock distributionfunction with subpicosecond jitter performance, along with anon-chip PLL and VCO. The on-chip VCO tunes from 2.02 GHzto 2.335 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHzcan also be used.The AD9520-2 serial interface supports both SPI and I2C?ports.An in-package EEPROM, which can be programmed through theserial interface, can store user-defined register settings forpower-up and chip reset.The AD9520-2 features 12 LVPECL outputs in four groups. Anyof the 1.6 GHz LVPECL outputs can be reconfigured as two250 MHz CMOS outputs. If an application requires LVDSdrivers instead of LVPECL drivers, refer to the AD9522-2.Each group of three outputs has a divider that allows both thedivide ratio (from 1 to 32) and the phase offset or coarse timedelay to be set.The AD9520-2 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. The external VCO can have anoperating voltage of up to 5.5 V. A separate output driver powersupply can be from 2.375 V to 3.465 V.The AD9520-2 is specified for operation over the standardindustrial range of ?40?C to +85?C.Applications Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures