The ADF4368 is a high performance, ultralow jitter, integer-N and fractional-N phase-locked loop (PLL) with integrated VCO ideally suited for frequency conversion applications.The high performance PLL has a figure of merit of -239dBc/Hz, very low 1/f Noise of normalized -287dBc/Hz and high PFD frequency that can achieve ultralow in-band noise and integrated jitter. The ADF4368 can generate any frequency from 800 MHz to 12.8 GHz without an internal doubler, thereby eliminating the need for sub-harmonic filters. Σ-Δ modulator includes a 25-bit fixed modulus which allows hertz frequency resolution and an additional 24-bit variable modulus which allows even finer resolution and flexibility for frequency planning. 9 dBm output power at 12.8 GHz in single ended configuration with 16 step power adjust feature makes it very useful for any application.For multiple frequency conversion applications such as phase array radar or massive MIMO systems, the outputs of multiple ADF4368 can be aligned by using SYNC input or EZSync. EZSync method is used when it is difficult to distribute the SYNC signal to all parts precisely. For applications that require deterministic delay or delay adjustment capability, a programmable reference to output delay with The simplicity of the ADF4368 block diagram eases development time with a simplified SPI register map, external SYNC input and repeatable multi-chip phase alignment both in integer and fractional mode.APPLICATIONSWireless infrastructure (MC-GSM, 5G)Test and MeasurementAerospace and Defense

The HMC833LP6GE is a low noise, wide band, Fractional-N Phase-Locked-Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO) with a fundamental frequency of 1500 MHz - 3000 MHz, and an integrated VCO Output Divider (divide by 1/2/4/6.../60/62) and doubler, that together allow the HMC833LP6GE to generate frequencies from 25 MHz to 6000 MHz. The integrated Phase Detector (PD) and delta-sigma modulator, capable of operating at up to 100 MHz, permit wider loop-bandwidths with excellent spectral performance.The HMC833LP6GE features industry leading phase noise and spurious performance, across all frequencies, that enable it to minimize blocker effects, and improve receiver sensitivity and transmitter spectral purity. The superior noise floor (< -170 dBc/Hz) makes the HMC833LP6GE an ideal source for a variety of applications - such as; LO for RF mixers, a clock source for high-frequency data-converters, or a tunable reference source for ultra-low spurious applications.Additional features of the HMC833LP6GE include RF output power control from 0 to 9 dB (3 dB steps), output Mute function, and a delta-sigma modulator Exact Frequency Mode which enables users to generate output frequencies with 0 Hz frequency error.Applications Cellular Infrastructure Microwave Radio WiMax, WiFi Communications Test Equipment CATV Equipment DDS Replacement Military Tunable Reference Source for?Spurious- Free Performance

The ADF4371 allows implementation of fractional-N or Integer N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. The wideband microwave voltage controlled oscillator (VCO) design allows frequencies from 62.5 MHz to 32 GHz to be generated.The ADF4371 has an integrated VCO with a fundamental output frequency ranging from 4000 MHz to 8000 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allows the user to generate radio frequency (RF) output frequencies as low as 62.5 MHz at RF8x. A frequency multiplier at RF16x generates from 8 GHz to 16 GHz. A frequency quadrupler generates frequencies from 16 GHz to 32 GHz at RF32x. RFAUX8x duplicates the frequency range of RF8x or permits direct access to the VCO output. To suppress the unwanted products of frequency multiplication, a harmonic filter exists between the multipliers and the output stages of RF16x and RF32x.Control of all on-chip registers is through a 3-wire interface. The ADF4371 operates with analog and digital power suppliesranging from 3.15 V to 3.45 V, and 5 V for the VCO power supply. The ADF4371 also contains hardware and software power-down modes. APPLICATIONS Wireless infrastructure (multicarrier global system for mobile communication (MC-GSM), 5 G) Test equipment and instrumentation Clock generation Aerospace and defense

The AD9531 provides a multioutput clock generator function and three on-chip phase-locked loop (PLL) cores with SPI programmable output frequencies and formats.PLL1 provides two reference inputs and 10 outputs and includes four user selectable loop configurations. The PLL has a fully integrated loop filter requiring only a single external capacitor (or a series RC network). PLL1 provides a wide range of output frequencies up to 400 MHz and is capable of operating with an external voltage controlled crystal oscillator (VCXO) and loop filter, instead of the integrated voltage controlled oscillator (VCO) and loop filter.PLL2 is an integer-N PLL providing a single reference input and 12 outputs. PLL2 synthesizes output frequencies up to 400 MHz from the REF2_x source and synchronizes the output clocks to the input reference.PLL3 provides a single reference input and two outputs. PLL3 synthesizes output frequencies up to 400 MHz from the REF3_x source and synchronizes the output clocks to input reference.The AD9531 is available in an 88-lead LFCSP and is specified over the −40°C to +85°C operating temperature range.Throughout this data sheet, multifunction pins, such as LOR/M4, are referred to either by the entire pin name or by a single function of the pin (for example, LOR, when only that function is relevant). In other cases, the text and figures of this data sheet contain references to a channel rather than a pin. For example, REF_A refers to the REF_A channel rather than the REF_AP and REF_AN pins. Likewise, OUT3_1 refers to Channel 1 of PLL3 rather than the OUT3_1P and OUT3_1N pins. Additionally, an abbreviated notation for a pin pair replaces an explicit reference to a each pin (for example, REF_Ax signifies the REF_AN and REF_AP pins.).Applications Radio equipment controller clocking Low jitter/phase noise clock generation and distribution Clock generation and translation for SONET, 10GE, 10G FC, and other 10 Gbps protocols 40 Gbps/100 Gbps networking line cards, including SONET, synchronous ethernet, OTU2/3/4 Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures Ethernet line cards, switches, and routers SATA and PCI-express

The AD9510 provides a multi-output clock distribution functionalong with an on-chip phase-locked loop (PLL) core. The designemphasizes low jitter and phase noise to maximize data converterperformance. Other applications with demanding phase noiseand jitter requirements also benefit from this device.The PLL section consists of a programmable reference divider(R); a low noise, phase frequency detector (PFD); a precisioncharge pump (CP); and a programmable feedback divider (N).By connecting an external voltage-controlled crystal oscillator(VCXO) or voltage-controlled oscillator (VCO) to the CLK2and CLK2B pins, frequencies of up to 1.6 GHz can be synchronizedto the input reference.There are eight independent clock outputs. Four outputs are lowvoltage positive emitter-coupled logic (LVPECL) at 1.2 GHz,and four are selectable as either LVDS (800 MHz) or CMOS(250 MHz) levels.Each output has a programmable divider that can be bypassedor set to divide by any integer up to 32. The phase of one clockoutput relative to another clock output can be varied by meansof a divider phase select function that serves as a coarse timingadjustment. Two of the LVDS/CMOS outputs feature programmabledelay elements with full-scale ranges up to 8 ns of delay.This fine tuning delay block has 5-bit resolution, giving 25possible delays from which to choose for each full-scale setting(Register 0x36 and Register 0x3A = 00000b to 11000b).The AD9510 is ideally suited for data converter clockingapplications where maximum converter performance isachieved by encode signals with subpicosecond jitter.The AD9510 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. An external VCO, which requires anextended voltage range, can be accommodated by connectingthe charge pump supply (VCP) to 5.5 V. The temperature rangeis −40°C to +85°C.Applications Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and mixed-signal front ends (MxFEs) High performance wireless transceivers High performance instrumentation Broadband infrastructure

The ADF4360-2 is a fully integrated integer-N synthesizerand voltage-controlled oscillator (VCO). The ADF4360-2 isdesigned for a center frequency of 2000 MHz. In addition, adivide-by-2 option is available, whereby the user gets an RFoutput of between 925 MHz and 1085 MHz.Control of all the on-chip registers is through a simple 3-wireinterface. The device operates with a power supply rangingfrom 3.0 V to 3.6 V and can be powered down when not in use.Applications Wireless handsets (DECT, GSM, PCS, DCS, WCDMA) Test equipment Wireless LANs CATV equipment

The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout buffer optimized for low jitter and low power operation. Possible configurations range from 12 LVDS to 24 CMOS outputs, including combinations of LVDS and CMOS outputs. Three control lines are used to determine whether fixed blocks of outputs (three banks of four) are LVDS or CMOS outputs.The ADCLK854 offers two selectable inputs and a sleep mode feature. The IN_SEL pin state determines which input is fanned out to all the outputs. The SLEEP pin enables a sleep mode to power down the device.The inputs accept various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Table 8 provides interface options for each type of connection.This device is available in a 48-pin LFCSP package. It is specified for operation over the standard industrial temperature range of −40°C to +85°C.APPLICATIONSLow jitter clock distributionClock and data signal restorationLevel translationWireless communicationsWired communicationsMedical and industrial imagingATE and high performance instrumentation

The ADCLK948 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 Ω on-chip termination resistors. The inputs accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFx pin is available for biasing ac-coupled inputs. The ADCLK948 features eight full-swing emitter coupled logic(ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply.The output stages are designed to directly drive 800 mV eachside into 50 Ω terminated to VCC -2V for a total differential output swing of 1.6V. The ADCLK948 is available in a 32-lead LFCSP and specified for operation over the standard industrial temperature range of −40°C to +85°C.APPLICATIONS Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation

The LTC6951 is a high performance, low noise, Phase Locked Loop (PLL) with a fully integrated VCO. The low noise VCO uses no external components and is internally calibrated to the correct output frequency with no external system support.The clock generation section provides five outputs based on the VCO prescaler signal with individual dividers for each output. Four outputs feature very low noise, low skew CML logic. The fifth output is low noise LVDS. All outputs can be synchronized and set to precise phase alignment using the programmable delays.Choose the LTC6951-1 if any desired output frequency falls in the ranges 2.5GHz to 2.7GHz, 1.66GHz to 1.8GHz, or 1.25GHz to 1.35GHz. Choose the LTC6951 for all other frequencies.Applications High Performance Data Converter Clocking Wireless Infrastructure Test and Measurement

The HMC1165 is a monolithic microwave integrated circuit (MMIC), voltage controlled oscillator (VCO) that integrates a resonator, a negative resistance device, and a varactor diode, and features a half frequency output. Because of the monolithic construction of the oscillator, the output power and phase noise performance are excellent over temperature.The output power is 8 dBm typical from a 5 V supply voltage. The VCO is housed in a RoHS-compliant LFCSP and requires no external matching components.Applications Point to point and multipoint radios  Test equipment and industrial controls  Very small aperture terminals (VSATs)