4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: Three power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator On-chip bias voltage generator Low-side power switch General-purpose outputs Multiple filter options Internal temperature sensor Self and system calibration Sensor burnout detection Automatic channel sequencer Per channel configuration Power supply: 2.7 V to 3.6 V and ±1.8 V Independent interface power supply Power-down current: 5 μA maximum Temperature range: −40°C to +125°C 32-lead LFCSP/24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ESD: 4 kVAD7124-4-EP Supports defense and aerospace applications (AQEC standard) Download AD7124-4-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19614

Dual, 16-Bit, 2.8 GSPS, TxDAC+ Digital-to-Analog Converter Features: Support input data rate >2 GSPS Proprietary low spurious and distortion design SFDR = 82 dBc at dc IF, −9 dBFS Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Selectable 1×, 2×, 4×, or 8× interpolation filter Low power architecture Transmit enable function allows extra power saving and instant control of the output status High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Low power: 1.42 W at 1.6 GSPS full operating conditions 88-lead LFCSP with exposed pad

Quad, 16-Bit, 2.4 GSPS, TxDAC+ Digital-to-Analog Converter Features: Supports input data rates up to 1 GSPS Proprietary, low spurious and distortion design Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at 180 MHz IF Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at 180 MHz IF SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Input signal power detection High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Digital quadrature modulation using a numerically controlled oscillator (NCO) Nyquist band selection—mix mode Selectable 1×, 2×, 4×, and 8× interpolation filters Low power: 2.11 W at 1.6 GSPS, full operating conditions 88-lead, exposed pad LFCSP

DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84 GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel, 11-bit resolution 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1  Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel, 11-bit resolution 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1  Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

14-Bit, 3GSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs  Support for lane rates up to 16 Gbps per lane  1.65 W total power per channel at 3 GSPS (default settings)  Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation 2 integrated, wideband digital processors per channel 48-bit NCO  4 cascaded half-band filters  Phase coherent NCO switching Up to 4 channels available  Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither