32 A, Ultra Low Power, 24-Bit Sigma-Delta ADC with Integrated PGA and FIFO Features: Ultralow current consumption (typical): 32 μA: continuous conversion mode (gain = 128) 5 μA: duty cycling mode (ratio = 1/16) 0.5 μA: standby mode 0.1 μA: power-down mode Built-in features for system level power savings: Current saving duty cycle ratio: 1/4 or 1/16 Smart sequencer and per channel configuration minimizes host processor load Deep embedded FIFO minimizes host processor load (depth of 256 samples) Autonomous FIFO interrupt functionality, threshold detection Single supply as low as 1.71 V increasing battery length RMS noise: 25 nV rms at 1.17 SPS (gain = 128) – 48 nV/√Hz Up to 22 noise free bits (gain = 1) Output data rate: 1.17 SPS to 2.4 kSPS Operates from 1.71 V to 3.6 V single supply or ±1.8 V split supplies Band gap reference with 15 ppm/°C maximum drift PGA with rail-to-rail analog input Adaptable sensor interfacing functionality: Matched programmable excitation currents for RTDs On-chip bias voltage generator for thermocouples Low-side power switch for bridge transducers Sensor open wire detection Internal temperature sensor and oscillator Self and system calibration Flexible filter options Simultaneous 50 Hz/60 Hz rejection (on selected filter options) General-purpose outputs Diagnostic functionality Crosspoint multiplexed inputs 8 differential/16 pseudo differential inputs 5 MHz SPI (3-wire or 4-wire) Available in 35-ball, 2.74 mm × 3.6 mm WLCSP Temperature range: −40°C to +105°C

16-Bit, 16-Channel, 500 kSPS/1 MSPS, Easy Drive Multiplexed SAR ADC Features: Easy Drive Reduced analog input and reference drive requirements On-chip reference buffer (WLCSP only) Overvoltage protection up to 5 mA on each analog input Long acquisition phase, ≥71.5% (715 ns/1000 ns) of cycle time at 1 MSPS High performance Sample rate: 500 kSPS (AD4695) or 1 MSPS (AD4696) INL: ±1.0 LSB maximum Guaranteed 16-bit, no missing codes SINAD: 93 dB typical, fIN = 1 kHz Oversampled dynamic range: 111.2 dB, OSR = 64 Small footprint, high channel density 32-lead 5 mm × 5 mm LFCSP 36-ball 2.96 mm × 2.96 mm WLCSP Easy Drive features support system level designs with fewer components Enhanced digital functionality First conversion accurate, no latency or pipeline delay Fast conversion time and dual-/quad-SDO modes allow low SPI clock rates Customizable channel sequencer On-chip oversampling and decimation Threshold detection alerts Offset and gain correction Autonomous conversion (autocycle) mode 1.14 V to 1.98 V logic SPI Low power 8 mW at fS = 1 MSPS and 4 mW at fS = 500 kSPS 4 μW standby power dissipation with the internal LDO disabled Internal LDO enables 3.15 V to 5.5 V, single analog supply operation Wide operating temperature range: −40°C to +125°C

16-Bit, 16-Channel, 500 kSPS/1 MSPS, Easy Drive Multiplexed SAR ADC Features: Easy Drive Reduced analog input and reference drive requirements On-chip reference buffer (WLCSP only) Overvoltage protection up to 5 mA on each analog input Long acquisition phase, ≥71.5% (715 ns/1000 ns) of cycle time at 1 MSPS High performance Sample rate: 500 kSPS (AD4695) or 1 MSPS (AD4696) INL: ±1.0 LSB maximum Guaranteed 16-bit, no missing codes SINAD: 93 dB typical, fIN = 1 kHz Oversampled dynamic range: 111.2 dB, OSR = 64 Small footprint, high channel density 32-lead 5 mm × 5 mm LFCSP 36-ball 2.96 mm × 2.96 mm WLCSP Easy Drive features support system level designs with fewer components Enhanced digital functionality First conversion accurate, no latency or pipeline delay Fast conversion time and dual-/quad-SDO modes allow low SPI clock rates Customizable channel sequencer On-chip oversampling and decimation Threshold detection alerts Offset and gain correction Autonomous conversion (autocycle) mode 1.14 V to 1.98 V logic SPI Low power 8 mW at fS = 1 MSPS and 4 mW at fS = 500 kSPS 4 μW standby power dissipation with the internal LDO disabled Internal LDO enables 3.15 V to 5.5 V, single analog supply operation Wide operating temperature range: −40°C to +125°C

4-Channel, 4 MSPS, 12-Bit, Dual, Simultaneous Sampling SAR ADCs Features: 16-bit, 14-bit, or 12-bit dual simultaneous sampling SAR ADC Single-ended analog inputs 4-channel with 2:1 multiplexers Channel sequencer mode High throughput rate of up to 4 MSPS SNR (typical) 87.5 dB (AD7386), VREF = 3.3 V external 84 dB (AD7387), VREF = 3.3 V external 73.8 dB (AD7388) 93 dB with OSR = 8, VREF = 2.5 V internal (AD7386) On-chip oversampling functions INL (typical) ±1.5 LSB (AD7386) ±0.5 LSB (AD7387) ±0.2 LSB (AD7388) Resolution boost function 2.5 V internal reference at 10 ppm/°C (maximum) Alert function −40°C to +125°C temperature range 16-lead, 3 mm × 3 mm LFCSP

16-Bit, Isolated Sigma-Delta Modulator Features: 5 MHz to 20 MHz external clock input rate 16 bits, no missing codes Signal to noise ratio (SNR): 88 dB (typical) Effective number of bits (ENOB): 14.2 bits typical Typical offset drift vs. temperature: 1.6 μV/°C typical On-board digital isolator On-board reference See data sheet for additional featuresAD7403-EP supports defense and aerospace applications (AQEC standard) Download AD7403-EP data sheet Military temperature range: −55°C to +125°C Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/16625 DSCC Drawing Number

Dual 12-Bit CMOS DAC with Parallel Load Input Structure Features: Two 12-bit DACs in One Package DAC Ladder Resistance Matching: 0.5% Space Saving Skinny DIP and Suface Mount Packages 4-Quadrant Multiplication Low Gain Error (1 LSB max Over Temperature) Fast Interface Timing

CMOS Dual 8-Bit Buffered Multiplying DAC Features: On-Chip Latches for both DACs +12 V to +15 V Operation DACs matched to 1% Four Quadrant Multiplication TTL/CMOS Compatible from +12 V to +15 V Latch Free (Protection Schottkys not Required)

16-Bit 8/10-Channel, Low Voltage, Low Power, Sigma Delta ADC Features: 8-/10-Channel, High Resolution Σ-Δ ADCs 16-Bit Resolution Factory-Calibrated Single Conversion Cycle Setting Programmable Gain Front End Simultaneous 50 Hz and 60 Hz Rejection VREF Select™ Allows Absolute and Ratiometric Measurement Capability Operation Can Be Optimized for Analog Performance (CHOP = 0) or Channel Throughput (CHOP= 1)

3 V/5 V Low Power, Synchronous Voltage-to-Frequency Converter Features: Synchronous operation Full-scale frequency set by external system clock 8-lead SOT-23 and 8-lead MSOP packages 3 V or 5 V operation Low power: 3 mW (Typ) Nominal input range: 0 to VREF True –150 mV capability without charge pump VREF range: 2.5 V to VDD Internal 2.5 V reference 1 MHz max input frequency Selectable high impedance buffered input Minimal external components required

2.5 MSPS, 24-Bit, 100 dB Sigma-Delta ADC with On-Chip Buffer Features: 120 dB dynamic range at 78 kHz output data rate 100 dB dynamic range at 2.5 MHz output data rate 112 dB SNR at 78 kHz output data rate 100 dB SNR at 2.5 MHz output data rate 2.5 MHz maximum fully filtered output word rate Fully differential modulator input Programmable oversampling rate (8X to 256X) On-chip differential amplifier for signal buffering Low-pass finite impulse response (FIR) filter with default or user-programmable coefficients Modulator output mode Overrange alert bit Digital offset and gain correction registers