DC1133A-A: Demo Board for the LTC2242-12 12-Bit, 250Msps ADC.

DC1147A-E: Demo Board for the LTC6403-1 200MHz, Low Noise, Low Power Fully Differential Input/Output Amplifier/Driver

DC1190A-D: Demo Board for the LTC2361 250ksps, 12-Bit Serial ADCs in TSOT-23

DC1257B: Demo Board for the LTC6416 2GHz Low Noise Differential 16-Bit ADC Buffer

The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k ? 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS port after being stored in the integrated FIFO memory. It is optimized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. All necessary functions, including the sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution.The on-chip FIFO allows small snapshots of time to be captured via the ADC and read back at a lower rate. This reduces the constraints of signal processing by transferring the captured data at an arbitrary time and at a much lower sample rate. The FIFO can be operated in several user-programmable modes. In the single capture mode, the ADC data is captured when signaled via the SPI port or the use of the external FILL? pins. In the continuous capture mode, the data is loaded continuously into the FIFO and the FILL? pins are used to stop this operation.The data stored in the FIFO can be read back based on several user-selectable output modes. The DUMP pin can be asserted to output the FIFO data. The data stored in the FIFO can be accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit DDR LVDS interface. The maximum output throughput supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR LVDS mode and is internally limited to 1/8th of the maximum input sample rate. This corresponds to the maximum output data rate of 62.5 MHz at an input clock rate of 500 MSPS.The ADC requires a 1.9 V analog voltage supply and a differential clock for full performance operation. Output format options include twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced SiGe BiCMOS process, the device is available in a 56-lead LFCSP and is specified over the industrial temperature range (?40?C to +85?C). This product is protected by a U.S. patent.APPLICATIONS Wireless and wired broadband communications Communications test equipment Power amplifier linearizationPRODUCT HIGHLIGHTS High Performance ADC Core. Maintains 65.8 dBFS SNR at 500 MSPS with a 250 MHz input. Low Power. Consumes only 695 mW at 500 MSPS. Ease of Use. On-chip 16k FIFO allows the user to target the high performance ADC to the time period of interest and reduce the constraints of processing the data by transferring it at an arbitrary time and a lower sample rate. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.9 V supply simplifies system power supply design. Serial Port Control. Standard serial port interface supports configuration of the device and customization for the user?s needs. 1.9 V or 3.3 V SPI and Serial Data Port Operation.

The AD9081 mixed signal front end (MxFE?) is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores, and four 12-bit, 4 GSPS rate, RF analog-to-digital converter (ADC) cores. The AD9081 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) that have wide instantaneous bandwidth. The device features eight transmit and eight receive lanes that support 24.75 Gbps/lane JESD204C or 15.5 Gbps/lane JESD204B standards. The device also has an on-chip clock multiplier, and a digital signal processing (DSP) capability targeted at either wideband or multiband direct to RF applications. The DSP datapaths can be bypassed to allow a direct connection between the converter cores and the JESD204 data transceiver port. The device also features low latency loopback and frequency hopping modes targeted at phase array radar system and electronic warfare applications. Two models for the AD9081 are offered. The 4D4AC model supports the full instantaneous channel bandwidth, whereas the 4D4AB model supports a maximum instantaneous bandwidth of 600 MHz per channel by automatically configuring the DSP to limit the instantaneous bandwidth at startup.APPLICATIONS Wireless communications infrastructure Microwave point-to-point, E-band and 5G mmWave Broadband communications systems DOCSIS 3.1 and 4.0 CMTS Phased array radar and electronic warfare Electronic test and measurement systems

The AD9094 is an 8-bit, 1 GSPS, quad analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. The device is designed to sample wide bandwidth analog signals up to 1.4 GHz. The AD9094 is optimized for wide input bandwidth, a high sampling rate, high works linearity, and low power in a small package. The quad-ADC cores feature multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs that support a variety of user-selectable input ranges. An integrated voltage reference facilitates design considerations. The analog inputs and clock signals are differential inputs. Users can configure each pair of intermediate frequency (IF) receiver outputs onto either one or two lanes of JESD204B Subclass 1 or Subclass 0, high speed, serialized outputs, depending on the sample rate and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF?, SYNCINB?AB, and SYNCINB?CD input pins. The AD9094 has flexible power-down options that allow significant power savings when desired. To program the power down options, use the 1.8 V capable, serial port interface (SPI). The AD9094 is available in a Pb-free, 72-lead, lead frame chip scale package (LFCSP) and is specified over a junction temperature range of ?40?C to +105?C. This product may be protected by one or more U.S. or international patents. Note that throughout the data sheet, multifunction pins, such as PDWN/STBY, are referred to either by the entire pin name or by a single function of the pin, for example, PDWN, when only that function is relevant. PRODUCT HIGHLIGHTS Low power consumption per channel. JESD204B lane rate support up to 15 Gbps. Wide, full power bandwidth supports IF sampling of signals up to 1.4 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.APPLICATIONSLaser imaging, detection, and ranging (LIDAR)CommunicationsDigital oscilloscope (DSO)Ultrawideband satellite receiversInstrumentation

The AD9106 TxDAC? and waveform generator is a high performance, quad digital-to-analog converter (DAC) integrating on-chip pattern memory for complex waveform generation with a direct digital synthesizer (DDS). The DDS is a 12-bit output, up to 180 MHz master clock sinewave generator with a 24-bit tuning word allowing 10.8 Hz/LSB frequency resolution. The DDS has a single frequency output for all four DACs and independent programmable phase shift outputs for each of the four DACs.SRAM data can include directly generated stored waveforms, amplitude modulation patterns applied to DDS outputs, or DDS frequency tuning words.An internal pattern control state machine allows the user to program the pattern period for all four DACs as well as the start delay within the pattern period for the signal output on each DAC channel.Registers accessed using the serial peripheral interface (SPI) configure the digital waveform generator and load patterns into the SRAM.There are gain adjustment factors and offset adjustments applied to the digital signals on their way into the four DACs.The AD9106 offers exceptional ac and dc performance and supports DAC sampling rates up to 180 MSPS. The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9106 make it well suited for portable and low power applications.Applications Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators

The AD9114/AD9115/AD9116/AD9117 are pin-compatible dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC? converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost.The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and dc performance and support update rates up to 125 MSPS.The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9114/AD9115/AD9116/AD9117 make them well suited for portable and low power applications.PRODUCT HIGHLIGHTS Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 225 mW at 100 MSPS. Sleep and power-down modes are provided for low power idle periods. CMOS Clock Input. High speed, single-ended CMOS clock input supports a 125 MSPS conversion rate. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows for easy interfacing to other components that accept common-mode levels greater than 0 V.?APPLICATIONS Wireless infrastructures Picocell, femtocell base stations Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators

The AD9121 is a dual, 14-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1230 MSPS, permitting multicarrier generation up to the Nyquist frequency.The AD9121 TxDAC+? includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9121 comes in a 72-lead LFCSP.PRODUCT HIGHLIGHTS Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies (IF). Proprietary DAC output switching technique enhances dynamic performance. Current outputs are easily configured for various single-ended or differential circuit topologies. Flexible LVDS digital interface allows the standard 28-wire bus to be reduced to one-half of the width.APPLICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point