The AD9119/AD9129 are high performance, 11-/14-bit RF digital-to-analog converters (DACs) supporting data rates up to 2.85 GSPS. The DAC core is based on a quad-switch architecture that enables dual-edge clocking operation, effectively increasing the DAC update rate to 5.7 GSPS when configured for Mix-Mode? or 2? interpolation. The high dynamic range and bandwidth enable multicarrier generation up to 4.2 GHz.In baseband mode, wide bandwidth capability combines with high dynamic range to support from 1 to 158 contiguous carriers for CATV infrastructure applications. A choice of two optional 2? interpolation filters is available to simplify the postreconstruction filter by effectively increasing the DAC update rate by a factor of 2. In Mix-Mode operation, the AD9119/AD9129 can reconstruct RF carriers in the second and third Nyquist zone while still maintaining exceptional dynamic range up to 4.2 GHz. The high performance NMOS DAC core features a quad-switch architecture that enables industry-leading direct RF synthesis performance with minimal loss in output power. The output current can be programmed over a range of 9.5 mA to 34.4 mA.The AD9119/AD9129 include several features that may further simplify system integration. A dual-port, source synchronous LVDS interface simplifies the data interface to a host FPGA/ASIC. A differential frame/parity bit is also included to monitor the integrity of the interface. On-chip delay locked loops (DLLs) optimize timing between different clock domains.A serial peripheral interface (SPI) configures the AD9119/ AD9129 and monitors the status of readback registers. The AD9119/AD9129 are manufactured on a 0.18 ?m CMOS process and operates from +1.8 V and ?1.5 V supplies. It is supplied in a 160-ball chip scale package ball grid array.Product Highlights High dynamic range and signal reconstruction bandwidth support RF signal synthesis of up to 4.2 GHz. Dual-port interface with double data rate (DDR) LVDS data receivers supports 2850 MSPS maximum conversion rate. Manufactured on a CMOS process; a proprietary switching technique enhances dynamic performance.Applications Broadband communications systems CMTS/VOD Wireless infrastructure: W-CDMA, LTE, point-to-point Instrumentation, automatic test equipment (ATE) Radar, jammers

The AD9146 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1230 MSPS, permitting multicarrier generation up to the Nyquist frequency.The AD9146 TxDAC+? includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 3-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9146 comes in a 48-lead LFCSP.PRODUCT HIGHLIGHTS Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. A proprietary DAC output switching technique enhances dynamic performance. The current outputs are easily configured for various single-ended or differential circuit topologies. Compact LVDS digital interface offers reduced width data bus.APPILICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point

The AD9161 is a high performance, 11-bit digital-to-analog converter (DAC) that supports data rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2? interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications.In baseband mode, wide bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of two carriers to full maximum spectrum of 1.794 GHz. A 2? interpolator filter (FIR85) enables the AD9161/AD9162 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode? operation, the AD9161/AD9162 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9161/AD9162 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.A serial peripheral interface (SPI) can configure the AD9161/AD9162 and monitor the status of all registers. The AD9161/AD9162 are offered in an 165-ball, 8.0 mm ? 8.0 mm, 0.5 mm pitch, CSP_BGA package and in an 169-ball, 11 mm ? 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option for the AD9162.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz. Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed. Bandwidth and dynamic range to meet DOCSIS 3.1 compliance with margin.Applications Broadband communications systems DOCSIS 3.1 cable modem termination system (CMTS)/video on demand (VOD)/edge quadrature amplitude modulation (EQAM) Wireless communications infrastructure W-CDMA, LTE, LTE-A, point to point Instrumentation, automatic test equipment (ATE) Radars and jammers

DC1257B: Demo Board for the LTC6416 2GHz Low Noise Differential 16-Bit ADC Buffer

The LTC2209 is a 160Msps 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 700MHz. The input range of the ADC can be optimized with the PGA front end.The LTC2209 is perfect for demanding communications applications, with AC performance that includes 77.3dBFS Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 70fsRMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ?5.5LSB INL, ?1LSB DNL (no missing codes).The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed busses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.The ENC+ and ENC? inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.Applications Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems

DC1287A: Demo Board for LTC6416 2GHz Low Noise Differential 16-Bit ADC Buffer

Demonstration circuit 1333A features the LTC2640, a 12-bit SPI DAC. This device establishes a new benchmark for size and integration of 12-bit DACs and onboard reference.

Demonstration circuit 1333A features the LTC2640, a 12-bit SPI DAC. This device establishes a new benchmark for size and integration of 12-bit DACs and onboard reference.

DC1369A-F: Demo Board for the LTC2256-14 14-Bit, 25Msps Ultralow Power 1.8V ADCs

DC1369A-H: Demo Board for the LTC2260-12 12-Bit, 105Msps Ultralow Power 1.8V ADCs