1MSPS, 4mW Internal Ref & Clk, 12-Bit Parallel ADC Features: Specified for VDD of 2.7 V to 5.25 V Throughput Rate of 1 MSPS—AD7492 Throughput Rate of 1.25 MSPS—AD7492-5 Low Power: 4 mW Typ at 1 MSPS with 3 V Supplies 11 mW Typ at 1 MSPS with 5 V Supplies Wide Input Bandwidth 70 dB Typ SNR at 100 kHz Input Frequency 2.5 V Internal Reference On-Chip CLK Oscillator Flexible Power/Throughput Rate Management No Pipeline Delays High-Speed Parallel Interface Sleep Mode: 50 nA Typ 24-Lead SOIC and TSSOP Packages

8-Bit Analog-to-Digital Converter Features: 8-Bit Resolution No Missed Codes over Full Temperature Range Fast Conversion Time: 15 µs Interfaces to µP like RAM, ROM of Slow - Memory Low Power Dissipation: 30 mW Ratiometric Capability Single +5V Supply Low Cost Internal Comparator and Clock Oscillator

16-Bit, 250 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC Features: Multiple pins/software programmable input ranges: 5 V, 10 V, ±5 V, ±10 V Pins or serial SPI®-compatible input ranges/mode selection Throughput: 250 kSPS 16-bit resolution with no missing codes INL: ±0.75 LSB typ, ±1.5 LSB max (±23 ppm of FSR) SNR: 94 dB @ 2 kHz iCMOS® process technology 5 V internal reference: typical drift 3 ppm/°C On-chip temperature sensor No pipeline delay (SAR architecture) Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Power dissipation 90 mW @ 250 kSPS 10 mW @ 1 kSPS 48-lead LQFP and LFCSP (7 mm × 7 mm) packages

12 Channel, 8-Bit TrimDACs with Power Shutdown & Separate VREFL Input Features: Low Cost Replaces 12 Potentiometers Individually Programmable Outputs Power Shutdown < 55 µWatts Including IDD & IREF 3-Wire SPI Compatible Serial Input Midscale Preset, AD8802 Separate VREF Range Settling, AD8804 +3 to +5 Single Supply Operation

Dual, 16-Bit, 1200 MSPS, TxDAC+Digital-to-Analog Converter Features: Flexible LVDS interface allows word, byte, or nibble load Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth Digital gain and phase adjustment for sideband suppression Multiple chip synchronization interfaces See data sheet for additional featuresAD9122-EP supports defense and aerospace applications (AQEC standard) Download AD9122-EP data sheet (pdf) Military temperature range (such as −55°C to +105°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/12654 DSCC Drawing Number

Quad, 16-Bit, 2.4 GSPS, TxDAC+ Digital-to-Analog Converter Features: Supports input data rates up to 1 GSPS Proprietary, low spurious and distortion design Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at 180 MHz IF Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at 180 MHz IF SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Input signal power detection High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Digital quadrature modulation using a numerically controlled oscillator (NCO) Nyquist band selection—mix mode Selectable 1×, 2×, 4×, and 8× interpolation filters Low power: 2.11 W at 1.6 GSPS, full operating conditions 88-lead, exposed pad LFCSP

16-Bit, 16-Channel, 500 kSPS/1 MSPS, Easy Drive Multiplexed SAR ADC Features: Easy Drive Reduced analog input and reference drive requirements On-chip reference buffer (WLCSP only) Overvoltage protection up to 5 mA on each analog input Long acquisition phase, ≥71.5% (715 ns/1000 ns) of cycle time at 1 MSPS High performance Sample rate: 500 kSPS (AD4695) or 1 MSPS (AD4696) INL: ±1.0 LSB maximum Guaranteed 16-bit, no missing codes SINAD: 93 dB typical, fIN = 1 kHz Oversampled dynamic range: 111.2 dB, OSR = 64 Small footprint, high channel density 32-lead 5 mm × 5 mm LFCSP 36-ball 2.96 mm × 2.96 mm WLCSP Easy Drive features support system level designs with fewer components Enhanced digital functionality First conversion accurate, no latency or pipeline delay Fast conversion time and dual-/quad-SDO modes allow low SPI clock rates Customizable channel sequencer On-chip oversampling and decimation Threshold detection alerts Offset and gain correction Autonomous conversion (autocycle) mode 1.14 V to 1.98 V logic SPI Low power 8 mW at fS = 1 MSPS and 4 mW at fS = 500 kSPS 4 μW standby power dissipation with the internal LDO disabled Internal LDO enables 3.15 V to 5.5 V, single analog supply operation Wide operating temperature range: −40°C to +125°C

Complete 12-Bit, 100 kHz, Sampling ADC (AD7870/AD7870A) Features: Complete Monolithic 12-Bit ADC with: 2 µs Track/Hold Amplifier 8 µs A/D Converter On-Chip Reference Laser-Trimmed Clock Parallel, Byte and Serial Digital Interface 57 ns Data Access Time 72 dB SNR at 10 kHz Input Frequency (AD7870, AD7875) Low Power: –60 mW typ Variety of Input Ranges: ±3 V for AD7870 0 V to +5 V for AD7875 ±10 V for AD7876

12 Bit Digital to Analog Converter 1 8-SO

Dual 12-Bit Complete DAC with Double Buffered Byte Loading Features: Complete Dual 12-Bit DAC Comprising Two 12-Bit CMOS DACs On-Chip Voltage Reference Output Amplifiers Reference Buffer Amplifiers Parallel Loading Structure: AD7247 (8 + 4) Loading Structure: AD7237 Single or Dual Supply Operation Low Power - 165 mW typ in Single Supply