Dual 14-Bit nanoDAC with 5 ppm/C On-Chip Reference Features: Low power, smallest pin-compatible, dual nanoDAC AD5663R: 16 bits AD5643R: 14 bits AD5623R: 12 bits User-selectable external or internal reference External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference 10-lead MSOP and 3 mm × 3 mm LFCSP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Serial interface up to 50 MHz Hardware LDAC and CLR functions

The AD7923 is a 12-bit, high speed, low power, 4-channel, successive-approximation (SAR) ADC. It operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 200 kSPS. It contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 8 MHz.The conversion process and data acquisition are controlled by CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and conversion is also initiated at this point.The AD7923 uses advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, it consumes 1.2 mA maximum with 3 V supplies and 1.5 mA maximum with 5 V supplies.Through the configuration of the control register, the analog input range can be selected as 0 V to REFIN or 0 V to 2 × REFIN, with either straight binary or twos complement output coding. The AD7923 features four single-ended analog inputs with achannel sequencer to allow a preprogrammed selection of channels to be converted sequentially.The conversion time for the AD7923 is determined by the serial clock, SCLK, frequency, since this is used as the master clock to control the conversion. The conversion time can be as short as 800 ns with a 20 MHz SCLK.

The AD4030-24/AD4032-24 are 2 MSPS or 500 kSPS successive approximation register (SAR), analog-to-digital converters (ADC) with Easy Drive™. With a guaranteed maximum ±0.9 ppm integral nonlinearity (INL) and no missing codes at 24-bits, the AD4030-24/AD4032-24 achieve unparalleled precision from −40°C to +125°C. Figure 1 shows the functional architecture of the AD4030-24/AD4032-24.A low drift, internal precision reference buffer eases voltage reference sharing with other system circuitry. The AD4030-24/AD4032-24 offer a typical dynamic range of 109 dB when using a 5 V reference. The low noise floor enables signal chains requiring less gain and lower power. A block averaging filter with programmable decimation ratio can increase dynamic range up to 155.5 dB. The wide differential input and common mode ranges allow inputs to use the full ±VREF range without saturating, simplifying signal conditioning requirements and system calibration. The improved settling of the Easy Drive analog inputs broadens the selection of analog front-end components compatible with the AD4030-24/AD4032-24. Both single-ended and differential signals are supported.The versatile Flexi-SPI serial peripheral interface (SPI) eases host processor and ADC integration. A wide data clocking window, multiple SDO lanes, and optional dual data rate (DDR) data clocking can reduce the serial clock to 10 MHz while operating at a sample rate of 2 MSPS or 500 kSPS. Echo clock mode and ADC host clock mode relax the timing requirements and simplify the use of digital isolators.The 7 mm × 7 mm, 64-Ball CSP_BGA package of the AD4030-24/AD4032-24 integrates all critical power supply and reference bypass capacitors, reducing the footprint and system component count, and lessening sensitivity to board layout.APPLICATIONS Automatic test equipment Digital control loops Medical instrumentation Seismology Semiconductor manufacturing Scientific instrumentation

The ADA4945-1 is a low noise, low distortion, fully differential amplifier with two selectable power modes. The device operates over a broad power supply range of 3 V to 10 V. The low dc offset, dc offset drift, and excellent dynamic performance of the ADA4945-1 makes it well suited for a variety of data acquisition and signal processing applications. The device is an ideal choice for driving high resolution, high performance successive approximation register (SAR) and Σ-Δ analog-to-digital converters (ADCs) on 4 mA of quiescent current (full power mode). The device can also be selected to operate on 1.4 mA of quiescent current (low power mode) to scale the power consumption to the desired performance necessary for an ADC drive application. The adjustable common-mode voltage allows the ADA4945-1 to match the input common-mode voltage of multiple ADCs. The internal common-mode feedback loop provides exceptional output balance, as well as suppression of even order harmonic distortion products.With the ADA4945-1, differential gain configurations are achieved with a simple external feedback network of four resistors determining the closed-loop gain of the amplifier. The ADA4945-1 is fabricated using Analog Devices, Inc., proprietary, silicon germanium (SiGe), complementary bipolar process, enabling the device to achieve low levels of distortion with an input voltage noise of only 1.8 nV/√Hz (full power mode).The ADA4945-1 is available in a RoHS-complaint, 3 mm × 3 mm, 16-lead LFCSP. The ADA4945-1 is specified to operate from −40°C to +125°C.Applications Low power Σ-Δ, PulSAR®, and SAR ADC drivers Single-ended to differential converters Differential buffers Medical imaging Process control Portable electronics

18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential analog input range 0 V to VREF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±3.2 LSB maximum Guaranteed 18-bit, no missing codes SNR: 95 dB at fIN = 1 kHz at VREF = 5 V THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 98 dB for OSR = 2 125 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

24-Bit, 4-Channel Simultaneous Sampling 1.5 MSPS Precision Alias Free ADC Features: Recommended pin to pin extended temperature range upgrade AD4134 Alias free: inherent antialias rejection of 102.5 dB typical in high performance mode Excellent ac and dc performance 108 dB dynamic range at ODR = 374 kSPS, FIR filter, typical 137 dB dynamic range at ODR = 10 SPS, sinc3 filter, typical THD: −120 dB typical with 1 kHz input tone Offset error drift: 0.7 µV/°C typical Gain drift: 2 ppm/°C typical INL: ±2 ppm of FSR typical Dynamic range enhancement: 4:1 and 2:1 averaging mode 126 dB, A weighted dynamic range Resistive ADC and reference input Easy to sync: asynchronous sample rate converter Multidevice synchronization with one signal line Programmable data rates from 0.01 kSPS to 1496 kSPS with resolution of 0.01 SPS Option to control output data rate by external signal Linear phase digital filter options Low ripple FIR filter: 32 µdB pass-band ripple, dc to 161.942 kHz Low latency sinc3 filter and sinc6 filter, dc to 391.5 kHz Sinc3 filter with 50 Hz/60 Hz rejection Crosstalk: 130.7 dBFS Daisy-chaining CRC error checking on data and SPI interface Two power modes: high performance mode and low power mode Power supply: 4.5 V to 5.5 V and 1.65 V to 1.95V 1.8 V IOVDD level External reference: 4.096 V or 5V Crystal or external CMOS clock of 48 MHz SPI or pin (standalone) configurable operation Operating temperature range: 0°C to 85°C Available in 8 mm × 8 mm, 56-lead LFCSP with exposed pad

Tiny 16-Bit I2C nanoDAC+, with 2 (16-Bit) LSB INL and 2 ppm/C Reference Features: Ultrasmall package: 2 mm × 2 mm, 8-lead LFCSP High relative accuracy (INL): ±2 LSB maximum at 16 bits Low drift, 2.5 V reference: 2 ppm/°C typical Selectable span output: 2.5 V or 5 V Total unadjusted error (TUE): ±0.06% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.05 % of FSR maximum Low glitch: 0.1 nV-sec High drive capability: 20 mA Low power: 1.2 mW at 3.3 V 1.8 V VLOGIC compatible Wide operating temperature range: −40°C to +105°C

Tiny 16-Bit I2C nanoDAC+, with 2 (16-Bit) LSB INL and 2 ppm/C Reference Features: Ultrasmall package: 2 mm × 2 mm, 8-lead LFCSP High relative accuracy (INL): ±2 LSB maximum at 16 bits Low drift, 2.5 V reference: 2 ppm/°C typical Selectable span output: 2.5 V or 5 V Total unadjusted error (TUE): ±0.06% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.05 % of FSR maximum Low glitch: 0.1 nV-sec High drive capability: 20 mA Low power: 1.2 mW at 3.3 V 1.8 V VLOGIC compatible Wide operating temperature range: −40°C to +105°C

14-Bit, 2.0 GSPS/2.6 GSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Support for lane rates up to 16 Gbps per lane Noise density −152 dBFS/Hz at 2.56 GSPS at full-scale voltage = 1.7 V p-p −154 dBFS/Hz at 2.56 GSPS at full-scale voltage = 2.0 V p-p −154.2 dBFS/Hz at 2.0 GSPS at full-scale voltage = 1.7 V p-p −155.3 dBFS/Hz at 2.0 GSPS at full-scale voltage = 2.0 V p-p 1.55 W total power per channel at 2.56 GSPS (default settings) SFDR at 2.56 GSPS encode 73 dBFS at 1.8 GHz AIN at −2.0 dBFS 59 dBFS at 5.53 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p SNR at 2.56 GSPS encode 59.7 dBFS at 1.8 GHz AIN at −2.0 dBFS 53.0 dBFS at 5.53 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p SFDR at 2.0 GSPS encode 78 dBFS at 900 MHz AIN at −2.0 dBFS 62 dBFS at 5.53 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p SNR at 2.0 GSPS encode 62.7 dBFS at 900 MHz AIN at −2.0 dBFS 53.1 dBFS at 5.5 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation Programmable FIR filters for analog channel loss equalization 2 integrated, wideband digital processors per channel 48-bit NCO Programmable decimation rates Phase coherent NCO switching Up to 4 channels available Serial port control Supports 100 MHz SPI writes and 50 MHz SPI reads Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither

Dual 14B Low Power D-A Converter