IC 12BIT DAC 7943 DIP16; Resolution (Bits):12bit; Sampling Rate:1.7MSPS; Input Channel Type:Serial; Supply Voltage Range:3V to 5.5V 4.5V to 5.5V; ADC / DAC Case Style:DIP; No. of Pins:16Pins; Data Interface:Serial; Operating Temperature Min:-40°C; Operating Temperature Max:85°C; Packaging:Each; Product Range:AD7943 Series; Automotive Qualification Standard:-; MSL:-; SVHC:No SVHC (20-Jun-2016); A/D / D/A Features:Multiplying 3.3V/5V; Base Number:7943; Conversion Time:0.6µs; IC Case Style:DIP; IC Generic Number:7943; Linearity Error:0.5%; Linearity Error ADC / DAC +:0.5LSB; Linearity Error ADC / DAC -:0.5LSB; Logic Function Number:7943; No. of Bits:12bit; No. of Channels:1Channels; Operating Temperature Range:-40°C to +85°C; Output Type:Current; Power Dissipation Ptot Max:670mW; Settling Time:0.6µs; Supply Current:5µA; Supply Voltage Max:5.5V; Supply Voltage Min:3V; Termination Type:Through Hole

Dual 14B Low Power D-A Converter

16 Bit 6GSPS RF DAC &DDS w/interpolation ;RoHS Compliant: Yes

Dual 10-Bit nanoDAC with 2 ppm/C Reference, I2C Interface Features: Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility Low glitch: 0.5 nV-sec 400 kHz I2C-compatible serial interface See data sheet for additional features

Dual 12-Bit DACPORT with Parallel Load Features: Complete Dual 12-Bit DAC Comprising Two 12-Bit CMOS DACs On-Chip Voltage Reference Output Amplifiers Reference Buffer Amplifiers Parallel Loading Structure: AD7247A Improved AD7237/AD7247: 12 V to 15 V Operation Faster Interface –30 ns typ Data Setup Time (8+4) Loading Structure: AD7237A Single or Dual Supply Operation Low Power—165 mW typ in Single Supply

Dual Channel, 16-Bit, 16 MUPS, Multispan, Multi-IO SPI DAC Features: 16-bit resolution 16 MUPS single channel rate in fast mode 11 MUPS single channel rate in precision mode 78 ns small signal settling time to 0.1% accuracy 100 ns large signal settling time to 0.1% accuracy Ultrasmall glitch: <50 pV×s Ultralow latency: 5 ns THD: −105 dB at 1 kHz Highly configurable output voltage span and offset 1.2 V and 1.8 V logic level compatible Single (classic) and dual SPI modes Multiple error detectors, both analog and digital domains 2.5 V internal voltage reference, 10 ppm/°C maximum temperature coefficient Small package: 4 mm × 4 mm LFCSP

18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential analog input range 0 V to VREF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±3.2 LSB maximum Guaranteed 18-bit, no missing codes SNR: 95 dB at fIN = 1 kHz at VREF = 5 V THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 98 dB for OSR = 2 125 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

Single Supply, 24-Bit, Sigma-Delta ADC with 10 V, 10 M Inputs and Buffered Low Level Inputs Features: 24-bit ADC with integrated analog front end Fast and flexible output rate: 1.25 SPS to 62.5 kSPS Channel scan data rate 12,422 SPS per channel (80 μs settling, sinc5 + sinc1) 20,618 SPS per channel (48 μs settling, sinc3) 85 dB rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, 6 differential or 11 single-ended Pin absolute maximum rating: ±65 V Absolute input pin voltage up to ±20 V ≥10 MΩ impedance Low level direct ADC input ±VREF inputs, 2 differential or 4 single-ended Absolute input pin voltage, AVDD to AVSS True rail-to-rail analog input buffers On-chip 2.5 V reference ±0.12% accuracy at 25°C, ±5 ppm/°C (typical) drift Internal or external clock Power supplies AVDD to AVSS = 4.5 V to 5.5 V IOVDD to DGND = 2 V to 5.5 V Total IDD (AVDD + IOVDD) = 6.15 mA Temperature range: −40°C to +105°C 3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK) SPI, QSPI, MICROWIRE, and DSP compatible

16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Port Features: 16-Bit Σ-Δ ADC Simultaneous 50 Hz and 60 Hz Rejection at 20 Hz Update Rate VREF Select™ Allows Absolute and Ratiometric Measurement Capability Programmable Gain Front End ISOURCE Select™ 16-Bit No Missing Codes 13-Bit p-p Resolution @ 20 Hz, 20 mV Range 16-Bit p-p Resolution @ 20 Hz, 2.56 V Range

DC to 204 kHz, Dynamic Signal Analysis, Precision 24-Bit ADC with Power Scaling Features:ADC for single-channel low power, platform DAQ designs Wide bandwidth Sinc filter bandwidth range: DC to 204 kHz Low ripple FIR bandwidth range: DC to 110.8 kHz Precision ac and dc performance 108.5 dB dynamic range typical −120 dB THD ±1.1 ppm of FSR INL, ±30 µV offset error, ±30 ppm of FSR gain error Programmable ODR, filter type, and latency ODR values up to 1024 kSPS Linear phase digital filter options Low ripple FIR filter: ±0.005 dB maximum pass-band ripple, dc to 102.4 kHz Low latency sinc5 filter Low latency sinc3 filter enabling 50 Hz/60 Hz rejection Programmable FIR filter option Programmable power consumption and bandwidth Fast, highest speed 52.224 kHz bandwidth, 26.4 mW (sinc5 filter) 110.8 kHz bandwidth, 36.8 mW (FIR filter) Median, half speed: 55.4 kHz bandwidth, 19.7 mW (FIR filter) Low power, low speed: 13.9 kHz bandwidth, 6.75 mW (FIR filter) Power supply AVDD1 − AVSS = 5.0 V typical AVDD2 − AVSS = 2.0 V to 5.0 V typical Analog supplies can run from split supply (true bipolar) IOVDD − DGND = 1.8 V to 3.3 V typical Low power mode can run from single 3.0 V supply Pin control or SPI interface configurable Suite of diagnostic check mechanisms Temperature, interface CRC, and memory map CRC Package: 28-lead, 4 mm × 5 mm, LFCSP Temperature range: −40°C to +125°C