Single Supply, 24-Bit, Sigma-Delta ADC with 10 V and 0 mA to 20 mA Inputs Features: Internal or external clock Tested for robustness per: IEC61000-4-2, IEC61000-4-3, IEC61000-4-4, IEC61000-4-5, IEC61000-4-6, CISPR 11 24-bit ADC with integrated analog front end Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS per channel (161 μs settling) 16 noise free bits at 1 kSPS per channel 85 dB rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, 4 differential or 8 single-ended Pin absolute maximum rating ±50 V Absolute input pin voltage up to ±20 V ≥1 MΩ impedance ±0.06% accuracy at 25°C 0 mA to 20 mA inputs, 4 single-ended Pin absolute maximum rating ±50 mA Input range from −0.5 mA to +24 mA 60 Ω impedance ±0.08% accuracy at 25°C On-chip 2.5 V reference ±0.12% accuracy at 25°C, ±5 ppm/°C (typical) drift Power supplies AVDD = 3.0 V to 5.5 V IOVDD = 2 V to 5.5 V Total IDD = 3.9 mA Temperature range: −40°C to +105°C 3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK) SPI, QSPI, MICROWIRE, and DSP compatible

Dual, 16-Bit, 6.2 GSPSRF DAC with SingleChannelizer Features: Supports single-band wireless applications 1 complex data input channel per RF DAC 516 MSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary,  low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane,  15.4 Gbps JESD204B interface Supports single-band use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 2×, 3×, 4×, and 6× configurable data channel interpolation 6× and 8× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 3.1 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 6.2 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 1.45 W at 6 GSPS, single-channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Octal, 16-Bit, SPI Voltage Output denseDAC With 5 ppm/C On-Chip Reference Features: Low power, small footprint, pin-compatible octal DACs: 16 bits 14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-ball WLCSP On-chip 1.25 V/2.5 V, 5 ppm/°C reference Power down to 400 nA at 5 V, 200 nA at 3 V 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale or midscale 3 power-down functions Hardware LDAC and LDAC override function CLR function to programmable code Rail-to-rail operationAD5668-EP supports defense and aerospace applications (AQEC standard) Download AD5668-EP data sheet (pdf) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/12643

Single, 16-Bit nanoDAC with 5 ppm/C On-Chip Reference Features: Low power, single nanoDAC AD5660: 16 bits 12-Bit Accuracy Guaranteed On-chip, 1.25 V/2.5 V, 5 ppm/°C reference Tiny 8-lead SOT-23/MSOP packages Power-down to 480 nA @ 5 V, 200 nA @ 3 V 3 V/5 V single power supply Guaranteed 16-bit monotonic by design Power-on reset to zero/midscale 3 power-down functions Serial interface with Schmitt-triggered inputs Rail-to-rail operation SYNC interrupt facility

8-Channel DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC Features: 8 simultaneously sampled inputs True bipolar analog input ranges: ±10 V, ±5 V Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 MΩ analog input impedance Second-order antialiasing analog filter On-chip accurate reference and reference buffer 18-bit ADC with 200 kSPS on all channels Oversampling capability with digital filter  Flexible parallel/serial interface SPI/QSPI™/MICROWIRE™/DSP compatible Pin compatible solutions from 14-bits to 18-bits Performance 7 kV ESD rating on analog input channels 98 dB SNR, −107 dB THD Low power: 100 mW Standby mode: 25 mW 64-lead LQFP package

Differential/Single-Ended Input, Dual, Simultaneous Sampling, 2 MSPS, 12-Bit, 3-Channel SAR A/D Converter Features: Dual 12-bit, 3-channel ADC Throughput rate: 2 MSPS Specified for VDD of 2.7 V to 5.25 V Power consumption: 9 mW at 1.5 MSPS with 3 V supplies 27 mW at 2 MSPS with 5 V supplies Pin-configurable analog inputs 12-channel single-ended inputs 6-channel fully differential inputs 6-channel pseudo differential inputs 70 dB SNR at 50 kHz input frequency Accurate on-chip reference: 2.5 V ±0.2% maximum @ 25°C, 20 ppm/°C maximum Dual conversion with read 437.5 ns, 32 MHz SCLK High speed serial interface SPI®-/QSPI™-/MICROWIRE&trade-/DSP-compatible −40°C to +125°C operation Shutdown mode: 1 μA maximum 32-lead LFCSP and 32-lead TQFP 1 MSPS version, AD7265

ANALOG TO DIGITAL CONVERTER ADC 12 BIT 2.5GSPS BGA-196; Resolution (Bits):12bit; Sampling Rate:2.5GSPS; Supply Voltage Type:-; Supply Voltage Min:2.4V; Supply Voltage Max:2.6V; ADC / DAC Case Style:BGA; No. of Pins:196; MSL:-

2.5 V to 5.5 V, 500 A, 2-Wire Interface Quad Voltage Output 10-Bit DAC Features: Four 10-Bit DACS in 10-Lead MicroSOIC Low Power: 600 µA @ 5 V, 500 µA @ 3 V Power-Down to 200 nA @ 5 V, 80nA @ 3 V Guaranteed Monotonic by Design Power-On-Reset to Zero Volts Three Power-Down Functions Double-Buffered Input Logic Output Range: 0 V to VREF 2-Wire (I2C™ Compatible) Data Readback Facility; Software Clear Facility Simultaneous Update via LDAC bit (active low) Temperature Range: −40°C to 105°C

144node maXTouch

144node maXTouch