Complete, Dual, 14-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DAC Features:Complete, dual, 14-bit digital-to-analog converter (DAC)Operates from single/dual suppliesSoftware programmable output range +5 V, +10 V, +10.8 V, 5 V, 10 V, 10.8 VINL error: 16 LSB maximum, DNL error: 1 LSB maximumTotal unadjusted error (TUE): 0.1% FSR maximumSettling time: 10 s typicalIntegrated reference buffersPlease see data sheet for additional features

Isolated Sigma-Delta Modulator Features: 20 MHz maximum external clock rate Second-order modulator 16 bits no missing codes ±2 LSB INL typical at 16 bits 3.5 μV/°C maximum offset drift On-board digital isolator On-board reference Low power operation: 20 mA maximum at 5.25 V −40°C to +105°C operating range 16-lead SOIC package Safety and regulatory approvals See Data Sheet for Addtional Features

Isolated Sigma-Delta Modulator Features: 10 MHz clock rate Second-order modulator 16 bits no missing codes ±2 LSB INL typical at 16 bits 3.5 μV/°C maximum offset drift On-board digital isolator On-board reference Low power operation: 18 mA maximum at 5.25 V −40°C to +105°C operating range 16-lead SOIC package See attached Data Sheet for more Features.

DC to 204 kHz, Dynamic Signal Analysis, Precision 24-Bit ADC with Power Scaling Features:ADC for single-channel low power, platform DAQ designs Wide bandwidth Sinc filter bandwidth range: DC to 204 kHz Low ripple FIR bandwidth range: DC to 110.8 kHz Precision ac and dc performance 108.5 dB dynamic range typical −120 dB THD ±1.1 ppm of FSR INL, ±30 µV offset error, ±30 ppm of FSR gain error Programmable ODR, filter type, and latency ODR values up to 1024 kSPS Linear phase digital filter options Low ripple FIR filter: ±0.005 dB maximum pass-band ripple, dc to 102.4 kHz Low latency sinc5 filter Low latency sinc3 filter enabling 50 Hz/60 Hz rejection Programmable FIR filter option Programmable power consumption and bandwidth Fast, highest speed 52.224 kHz bandwidth, 26.4 mW (sinc5 filter) 110.8 kHz bandwidth, 36.8 mW (FIR filter) Median, half speed: 55.4 kHz bandwidth, 19.7 mW (FIR filter) Low power, low speed: 13.9 kHz bandwidth, 6.75 mW (FIR filter) Power supply AVDD1 − AVSS = 5.0 V typical AVDD2 − AVSS = 2.0 V to 5.0 V typical Analog supplies can run from split supply (true bipolar) IOVDD − DGND = 1.8 V to 3.3 V typical Low power mode can run from single 3.0 V supply Pin control or SPI interface configurable Suite of diagnostic check mechanisms Temperature, interface CRC, and memory map CRC Package: 28-lead, 4 mm × 5 mm, LFCSP Temperature range: −40°C to +125°C

2.7 V to 5.5 V, Parallel Input Dual Voltage Output 8-Bit DAC Features: Two 8-Bit DACs in One Package 20-Lead DIP/SOIC/TSSOP Package +2.7 V to +5.5 V Operation Internal and External Reference Capability DAC Power-Down Function Parallel Interface On-Chip Output Buffer Rail-to-Rail Operation Low power Operation 3 mA max @ 3.3 V Power-Down to 1 µA max @ 25°C

500 kSPS, 8-Channel, Software Selectable True bipolar Input, 12-Bit Plus Sign A/D Converter Features: 12-bit plus sign SAR ADC True bipolar input ranges Software-selectable input ranges: ±10 V, ±5 V, ±2.5 V, 0 V to +10 V 500 kSPS throughput rate 8 analog input channels with channel sequencer Single-ended, true differential, and pseudo differential analog input capability See data sheet for additional featuresAD7327-EP supports defense and aerospace applications (AQEC standard) Download AD7327-EP data sheet (pdf) Military temperature range: −55°C to +125°C Controlled manufacturing baseline  One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/14636 DSCC Drawing Number

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

16-Bit, 15 MSPS, Module Data Acquisition Solution Features: Integrated fully differential ADC driver with signal scaling Wide input common-mode voltage range High common-mode rejection Single-ended to differential conversion Pin selectable input range with over-range Input Ranges with 4.096V REFBUF: ±10V, ±5V, ±4.096V, ±2.5V and ±1.5V Gain/Attenuation Options: 0.37, 0.73, 0.87, 1.38 and 2.25 Critical passive components 0.005% precision matched resistor array for FDA 9 mm × 9 mm, 0.8 mm pitch, 100-ball BGA package 2.5× footprint reduction versus discrete solution Low power, dynamic power scaling, power-down mode Throughput: 15 MSPS, no pipeline delay INL error: ±7.5 ppm typical, ±15 ppm maximum (Gain = 0.73, gain = 0.87, gain = 1.38, gain = 2.25) SINAD: 90 dB typical at 1 kHz (gain = 0.37 and gain = 0.73) THD: −121 dB at 1 kHz, −112 dB at 100 kHz (gain = 0.73) Gain error: ±0.005%FS typical Gain error drift: ±0.11 ppm/°C typical On-board reference buffer with VCMO generation Serial LVDS interface Wide operating temperature range: −40°C to +85°C

Variable Resolution, 10-Bit to 16-Bit R/D Converter with Reference Oscillator Features: Chinese data sheet available Complete monolithic resolver-to-digital converter 3125 rps maximum tracking rate (10-bit resolution and CLKIN = 10.24 MHz) ±2.5 (+ 1 LSB) arc minutes of angular accuracy (B and D grades) 10-/12-/14-/16-bit resolution, set by user Parallel and serial 10-bit to 16-bit data ports Absolute position and velocity outputs System fault detection Programmable fault detection thresholds Differential inputs Incremental encoder emulation Programmable sinusoidal oscillator on-board Compatible with DSP and SPI standards 5 V supply with 2.3 V to 5.25 V logic interface −40°C to +125°C temperature rating (C, D, and W grades) AEC-Q100 qualified for automotive applications ASIL B safety assessment certificate available Safety manual availableAD2S1210-EP supports defense and aerospace applications (AQEC standard) Download AD2S1210-EP Data Sheet (pdf) Military temperature range: (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available upon request V62/11604 DSCC Drawing Number

Universal Input Analog Front End with 24-Bit ADC for Industrial Process Control Systems Features: 2 software programmable input terminals Current up to ±20 mA Voltage up to ±10 V Thermocouple RTD Replaces existing 3-terminal solutions Field power supply for loop powered current sensors HV input overvoltage protected up to ±30 V Internal current sense resistor Option to use external current sense resistor Current limited input even with no power supply Diagnostic functions for overrange and open wire detect Fast and flexible output data rates: 5 SPS to 125 kSPS 16 noise free bits at 62 kSPS 18 noise free bits at 2.5 kSPS 20 noise free bits at 50 SPS/60 SPS Simultaneous 50 Hz and 60 Hz rejection Serial interface for configuration and diagnostics 4-wire interface compatible with SPI®, QSPI™, MICROWIRE®, and DSP Power supply: ±12 V to ±20 V, +5 V Operating temperature: −40°C to +105°C Package: 40-lead, 6 mm × 6 mm LFCSP