2.5 V to 5.5 V, 500 A, Quad Voltage Output 10-Bit DAC in 10-Lead Packages Features: 4 buffered 10-Bit DACs in 10-lead MSOP and 10-lead LFCSP A, W Version: ±4 LSB INL, B Version: ±2.5 LSB INL Low power operation: 500 µA @ 3 V, 600 µA @ 5 V 2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes Power-down to 80 nA @ 3 V, 200 nA @ 5 V Double-buffered input logic Output range: 0 V to VREF Power-on reset to 0 V Simultaneous update of outputs (LDAC function) Low power-, SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible 3-wire serial interface On-chip, rail-to-rail output buffer amplifiers Temperature range –40°C to +105°C Qualified for automotive applications

Quad 16-Bit nanoDAC+ with 2 ppm/C Reference, I2C Interface Features: High relative accuracy (INL): ±2 LSB maximum at 16 bits Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility Low glitch: 0.5 nV-sec 400 kHz I2C-compatible serial interface Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply −40°C to +105°C temperature range

8-Channel DAC with PLL and Differential Outputs, 192 kHz, 24 Bits Features:PLL generated or direct master clockLow EMI designDAC with 110 dB dynamic range and SNR96 dB THD + N3.3 V single supplyTolerance for 5 V logic inputsSupports 24 bits and 8 kHz to 192 kHz sample ratesDifferential DAC outputLog volume control with autoramp functionSPI controllable for flexibilitySoftware-controllable clickless muteSee data sheet for additional features

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

16-Channel, 1 MSPS, 12-Bit ADC with Sequencer Features: Fast throughput rate: 1 MSPS Specified for VDD of 2.7 V to 5.25 V Low power at maximum throughput rates 5.4 mW maximum at 870 kSPS with 3 V supplies 12.5 mW maximum at 1 MSPS with 5 V supplies 16 (single-ended) inputs with sequencer Wide input bandwidth: 69.5 dB SNR at 50 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface, SPI/QSPI™/MICROWIRE™/ DSP compatible Full shutdown mode: 0.5 μA maximum 28-lead TSSOP and 32-lead LFCSP packages AEC-Q100 qualified for automotive applicationsAD7490-EP supports defense and aerospace applications (AQEC standard) Download AD7490-EP Data Sheet (pdf) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/12635 DSCC Drawing Number

8-Channel DAS with 16-Bit, 800 kSPS Bipolar Input, Simultaneous Sampling ADC Features:16-bit ADC with 800 kSPS on all channels Input buffer with 5 M analog input impedance Pin to pin compatible with the AD7606 −40°C to +125°C operating temperature range Single 5 V analog supply and 1.71 V to 3.6 V VDRIVE supply ±21 V input clamp protection with 8 kV ESDExtra modes available in software mode Per channel selectable analog input ranges Single-ended, bipolar: ±10 V, ±5 V, and ±2.5 V Per channel system phase, offset, and gain calibration Analog input open circuit detection feature <20 LSB open circuit code error (RPD = 10 k) Self diagnostics and monitoring features CRC error checking on read/write data and registers

Quad, 12-Bit nanoDAC+ with I2C Interface Features: High relative accuracy (INL): ±2 LSB maximum at 16 bits Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User-selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility 400 kHz I2C-compatible serial interface 4 I2C addresses available Low glitch: 0.5 nV-sec Low power: 1.8 mW at 3 V 2.7 V to 5.5 V power supply −40°C to +105°C temperature range

Differential Input, 1 MSPS, 12-BIT SAR ADC Features: Fast Throughput Rate: 1 MSPS Specified for VDD of 3 V and 5 V Low Power at max Throughput Rate: - 3.75 mW max at 833 kSPS with 3 V Supplies - 9 mW max at 1MSPS with 5 V Supplies Fully Differential Analog Input Flexible Power/Serial Clock Speed Management Variable Reference Input Wide Input Bandwidth: 70dB SINAD at 300kHz Input Frequency No Pipeline Delays High Speed Serial Interface - SPI®/QSPI™/MicroWire™/DSP Compatible Powerdown Mode: 1µA max

Complete, Dual, 14-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DAC Features:Complete, dual, 14-bit digital-to-analog converter (DAC)Operates from single/dual suppliesSoftware programmable output range +5 V, +10 V, +10.8 V, 5 V, 10 V, 10.8 VINL error: 16 LSB maximum, DNL error: 1 LSB maximumTotal unadjusted error (TUE): 0.1% FSR maximumSettling time: 10 s typicalIntegrated reference buffersPlease see data sheet for additional features

Isolated Sigma-Delta Modulator Features: 20 MHz maximum external clock rate Second-order modulator 16 bits no missing codes ±2 LSB INL typical at 16 bits 3.5 μV/°C maximum offset drift On-board digital isolator On-board reference Low power operation: 20 mA maximum at 5.25 V −40°C to +105°C operating range 16-lead SOIC package Safety and regulatory approvals See Data Sheet for Addtional Features