12-Bit, 210 MSPS TxDAC D/A Converter Features: High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SNR at 5 MHz output, 125 MSPS: 70 dB Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA Power dissipation: 135 mW at 3.3 V Power-down mode: 15 mW at 3.3 V On-chip 1.2 V Reference CMOS compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP Edge-triggered latches

16-Bit, 100 kSPS, Parallel I/O A/D Converter Features: Fast 16-Bit ADC 100 kSPS Throughput Single 5 V Supply Operation Input Range: ±10 V 100 mW Max Power Dissipation Choice of External or Internal 2.5 V Reference High Speed Parallel Interface On-Chip Clock 28-Lead Skinny DIP, SSOP or SOIC Packages

16-Bit, 100 kSPS, Parallel I/O A/D Converter Features: Fast 16-Bit ADC 100 kSPS Throughput Single 5 V Supply Operation Input Range: ±10 V 100 mW Max Power Dissipation Choice of External or Internal 2.5 V Reference High Speed Parallel Interface On-Chip Clock 28-Lead Skinny DIP, SSOP or SOIC Packages

Dual 12-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO Features: Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Low power, fine complex NCO allows carrier placement anywhere in DAC bandwidth while adding <300 mW power Auxiliary DACs allow I and Q gain matching and offset control Includes programmable I and Q phase compensation Internal digital upconversion capability Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed pad TQFP package

4T4R Direct RF Receiver and Transmitter Features: Flexible, reconfigurable radio common platform design Transmitter/receiver channel bandwidth up to 1.2 GHz (4T4R) RF DAC/RF ADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RF clock input option Versatile digital features Selectable interpolation and decimation filters Configurable DDCs and DUCs 8 fine complex DUCs (FDUC) and 4 coarse complex DUCs (CDUC) 8 fine complex DDCs (FDDC) and 4 coarse complex DDCs (CDDC) FDUCs and FDDCs are fully bypassable 2 independent 48-bit NCOs per DUC or DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Supports real or complex digital data (8-, 12-, or 16-bit) Auxiliary features ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins support toggling between modes TDD power savings option and sharing ADCs SERDES JESD204B or JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver (JRx) Supports Subclass 1 Supports multidevice synchronization 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

EVALUATION KIT, DATA ACQUISITION;

Data Conversion IC Development Tools LTC2123 Demo Board - 14-bit, 250Msps Dua

The AD5330 / AD5331 / AD5340 / AD5341 are single 8-/10-/12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 115 μA at 3 V and feature a power-down mode that further reduces the current to 80 nA. The devices incorporate an on-chip output buffer that can drive the output to both supply rails, but the AD5330, AD5340, and AD5341 allow a choice of buffered or unbuffered reference input.The AD5330 / AD5331 / AD5340 / AD5341 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. The GAIN pin allows the output range to be set at 0 V to VREF or 0 V to 2 × VREF.Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin.An asynchronous CLR input is also provided, which resets the contents of the input register and the DAC register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device.The AD5330 / AD5331 / AD5340 / AD5341 are available in thin shrink small outline packages (TSSOP).APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process control

The AD5543/AD5553 are precision 16-/14-bit, low power, current output, small form factor digital-to-analog converters (DACs). They are designed to operate from a single 5 V supply with a ±10 V multiplying reference.The applied external reference, VREF, determines the full-scale output current. An internal feedback resistor (RFB) facilitates the R-2R and temperature tracking for voltage conversion when combined with an external operational amplifier.A serial data interface offers high speed, 3-wire microcontroller-compatible inputs using serial data in (SDI), clock (CLK), and chip select (CS).The AD5543/AD5553 are packaged in ultracompact (3 mm × 4.7 mm) 8-lead MSOP and 8-lead SOIC packages.Applications Automatic test equipment Instrumentation Digitally controlled calibration Industrial control programmable logic controllers

The AD660 DACPORT® is a complete 16-bit monolithic digital-to-analog converter with an on-board voltage reference, double-buffered latches, and an output amplifier. It is manufactured on the Analog Devices, Inc., BiMOS II process. This process allows the fabrication of low power CMOS logic functions on the same chip as high precision bipolar linear circuitry.The AD660 architecture ensures 15-bit monotonicity over time and temperature. Integral and differential nonlinearity is maintained at ±0.003% maximum. The on-chip output amplifier provides a voltage output settling time of 10 μs to within ½ LSB for a full-scale step.The AD660 has an extremely flexible digital interface. Data can be loaded into the AD660 in serial mode or as two 8-bit bytes. This is made possible by two digital input pins that have dual functions. The serial mode input format is pin selectable to be MSB or LSB first. The serial output pin allows the user to daisy-chain several AD660 devices by shifting the data through the input latch into the next DAC, thus minimizing the number of control lines required to SIN, CS and LDAC. The byte mode input format is also flexible in that the high byte or low byte data can be loaded first. The double buffered latch structure eliminates data skew errors and provides for simultaneous updating of DACs in a multiDAC system.The AD660 is available in five grades. AN and BN versions are specified from −40°C to +85°C and are packaged in a 24-lead300 mil plastic DIP. AR and BR versions are also specified from −40°C to +85°C and are packaged in a 24-lead SOIC. The SQ version is packaged in a 24-lead 300 mil CERDIP package and is also available compliant to MIL-STD-883. Refer to the AD660SQ/883B military data sheet for specifications and test conditions.PRODUCT HIGHLIGHTS The AD660 is a complete 16-bit DAC, with a voltage reference, double-buffered latches, and an output amplifier on a single chip. The internal buried Zener reference is laser trimmed to 10.000 V with a ±0.1% maximum error and a temperature drift performance of ±15 ppm/°C. The reference is available for external applications. The output range of the AD660 is pin programmable and can be set to provide a unipolar output range of 0 V to 10 V or a bipolar output range of −10 V to +10 V. No external components are required. The AD660 is both dc and ac specified. DC specifications include ±1 LSB INL and ±1 LSB DNL errors. AC specifications include 0.009% THD + N and 83 dB SNR. The double-buffered latches on the AD660 eliminate data skew errors and allow simultaneous updating of DACs in multiDAC applications. The clear function can asynchronously set the output to 0 V regardless of whether the DAC is in unipolar or bipolar mode. The output amplifier settles within 10 μs to ±½ LSB for a full-scale step and within 2.5 μs for a 1 LSB step over temperature. The output glitch is typically 15 nV-s when a full-scale step is loaded. Data Sheet, Rev. B, 6/08