The HMC948LP3E Logarithmic Detector converts RF signals at its input, to a proportional DC voltage at its output. The HMC948LP3E employs successive compression topology which delivers high dynamic range over a wide input frequency range. As the input power is increased, successive amplifiers move into saturation one by one creating an approximation of the logarithm function.The output of a series of square law detectors is summed, converted into the voltage domain and buffered to drive the LOG OUT output. The HMC948LP3E provides a nominal logarithmic slope of +14.2 mV/dB and an intercept of -111 dBm at 23 GHz. Ideal as a log detector for high volume microwave radio and VSAT applications, the HMC948LP3E is housed in a compact 3x3 mm RoHS compliant SMT plastic package.Applications Point-to-Point Microwave Radio VSAT Wideband Power Monitoring Receiver Signal Strength?Indication (RSSI) Test & Measurement

The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Applications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD8313 is a complete multistage demodulating logarithmic amplifier that can accurately convert an RF signal at its input to an equivalent decibel-scaled value at its dc output. The AD8313 maintains a high degree of log conformance for signal frequencies from 0.1 GHz to 2.5 GHz. Application is straightforward, requiring only a single supply of 2.7 V to 5.5 V and the addition of a suitable input and supply decoupling. Operating on a 3 V supply, its 13.7 mA consumption (for TA = 25?C) is only 41 mW. A power-down feature is provided; the input is taken high to initiate a low current (20 ?A) sleep mode, with a threshold at half the supply voltageThe AD8313 is fabricated on Analog Devices, Inc., advanced 25 GHz silicon bipolar IC process and is available in an 8-lead MSOP package. The operating temperature range is ?40?C to +85?C.

RF Amplifier 10 GHz gain block, Linr Drive/Gain Block

Phase Locked Loops - PLL WBand RF PLL VCO, 25-3000MHz

The HMC370LP4(E) is an active miniature x4 frequency multiplier utilizing InGaP GaAs HBT technology in a 4x4 mm leadless surface mount package. Power output is 0 dBm typical from a 5V supply voltage and varies little vs. input power, temperature and supply voltage. Suppression of undesired fundamental and sub-harmonics is >22 dBc typical with respect to output signal level. The low additive SSB phase noise of -140 dBc/Hz at 100 kHz offset helps the user maintain good system noise performance. The HMC370LP4(E) is ideal for use in LO multiplier chains allowing reduced parts count vs. traditional approaches.APPLICATIONS Point-to-Point & VSAT Radios Fiber Optic Military

The ADL5324 incorporates a dynamically adjustable biasing circuit that allows for the customization of OIP3 and P1dB performance from 3.3 V to 5 V, without the need for an external bias resistor. This feature gives the designer the ability to tailor driver amplifier performance to the specific needs of the design. This feature also creates the opportunity for dynamic biasing of the driver amplifier where a variable supply is used to allow for full 5 V biasing under large signal conditions, and then reduced supply voltage when signal levels are smaller and lower power consumption is desirable. This scalability reduces the need to evaluate and inventory multiple driver amplifiers for different output power requirements, from 25 dBm to 29 dBm output power levels.The ADL5324 is also rated to operate across the wide temperature range of ?40?C to +105?C for reliable performance in designs that experience higher temperatures, such as power amplifiers. The ? W driver amplifier also covers the wide frequency range of 400 MHz to 4000 MHz, and only requiresa few external components to be tuned to a specific band within that wide range. This high performance broadband RF driver amplifier is well suited for a variety of wired and wireless applications, including cellular infrastructure, ISM band power amplifiers, defense equipment, and instrumentation equipment. A fully populated evaluation board is available.The ADL5324 also delivers excellent ACPR vs. output power and bias voltage. The driver can deliver greater than 17 dBm of output power at 2140 MHz, while achieving an ACPR of ?55 dBc at 5 V. If the bias is reduced to 3.3 V, the ?55 dBc ACPR output power only minimally reduces to 15 dBm.Applications Wireless infrastructure Automated test equipment ISM/AMR applications

DC1431A-A: Demo Board for the LTC5540 600MHz to 1.3GHz High Dynamic Range Downconverting Mixer.

DC1431A-B: Demo Board for the LTC5541 1.3GHz to 2.3GHz High Dynamic Range Downconverting Mixer.

The ADAR1000 is a 4-channel, X and Ku frequency band, beamforming core chip for phased arrays. This device operates in half-duplex between receive and transmit modes. In receive mode, input signals pass through four receive channels and are combined and output at the common RF_IO pin. In transmit mode, the RF_IO input signal is split and passes through the four transmit channels. In both modes, the ADAR1000 provides a ?31 dB gain adjustment range and a full 360? phase adjustment range in each radio frequency (RF) channel, with 6-bit resolution (less than ?0.5 dB and 2.8?, respectively).A simple 4-wire serial port interface (SPI) controls all of the on-chip registers. In addition, two address pins allow SPI control of up to four devices on the same serial lines. Dedicated transmit and receive load pins also provide synchronization of all ADAR1000 chips in the same array, and a single pin controls fast switching between the transmit and receive modes. The ADAR1000 is fabricated in a silicon-germanium, bipolar CMOS (BiCMOS) process. The device is available in a compact, 88-terminal, 7 mm ? 7 mm, LGA package and is specified from ?40?C to +85?C.APPLICATIONS Phased array radar Satellite communications systems