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The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiver™ designed for use in 3G and 4G base station applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines a RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9361 receiver LO operates from 70 MHz to 6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported.

The two independent direct conversion receivers have state-of-the-art noise figure and linearity. Each receive (RX) subsystem includes independent automatic gain control (AGC), dc offset correction, quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband. The AD9361 also has flexible manual gain modes that can be externally controlled. Two high dynamic range analog-to-digital converters (ADCs) per channel digitize the received I and Q signals and pass them through configurable decimation filters and 128-tap finite impulse response (FIR) filters to produce a 12-bit output signal at the appropriate sample rate.

The transmitters use a direct conversion architecture that achieves high modulation accuracy with ultralow noise. This transmitter design produces a best in class TX error vector magnitude (EVM) of <−40 dB, allowing significant system margin for the external power amplifier (PA) selection. The on-board transmit (TX) power monitor can be used as a power detector, enabling highly accurate TX power measurements.

The fully integrated phase-locked loops (PLLs) provide low power fractional-N frequency synthesis for all receive and transmit channels. Channel isolation, demanded by frequency division duplex (FDD) systems, is integrated into the design. All VCO and loop filter components are integrated.

The core of the AD9361 can be powered directly from a 1.3 V regulator. The IC is controlled via a standard 4-wire serial port and four real-time input/output control pins. Comprehensive power-down modes are included to minimize power consumption during normal use. The AD9361 is packaged in a 10 mm × 10 mm, 144-ball chip scale package ball grid array (CSP_BGA).

Applications:

• Point to point communication systems
• Femtocell/picocell/microcell base stations
• General-purpose radio systems

Features:

• RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs
• TX band: 47 MHz to 6.0 GHz
• RX band: 70 MHz to 6.0 GHz
• Supports TDD and FDD operation
• Tunable channel bandwidth: <200 kHz to 56 MHz
• Dual receivers: 6 differential
• Superior receiver sensitivity with a noise figure of 2 dB at 800 MHz LO
• RX gain control
• Real-time monitor and control signals for manual gain
• Independent automatic gain control
• Dual transmitters: 4 differential outputs
• Highly linear broadband transmitter
  
  • TX EVM: ≤−40 dB
  • TX noise: ≤−157 dBm/Hz noise floor
  • TX monitor: ≥66 dB dynamic range with 1 dB accuracy
• Integrated fractional-N synthesizers
• 2.4 Hz maximum local oscillator (LO) step size
• Multichip synchronization
• CMOS/LVDS digital interface

The ADL5387 is a broadband quadrature I/Q demodulator that covers an RF/IF input frequency range from 30 MHz to 2 GHz. With a NF = 13.2 dB, IP1dB = 12.7 dBm, and IIP3 = 32 dBm @ 450 MHz, the ADL5387 demodulator offers outstanding dynamic range suitable for the demanding infrastructure direct-conversion requirements. The differential RF/IF inputs provide a well-behaved broadband input impedance of 50 Ω and are best driven from a 1:1 balun for optimum performance.Ultrabroadband operation is achieved with a divide-by-2 method for local oscillator (LO) quadrature generation. Over a wide range of LO levels, excellent demodulation accuracy is achieved with amplitude and phase balances ~0.05 dB and ~0.4°, respectively. The demodulated in-phase (I) and quadrature (Q) differential outputs are fully buffered and provide a voltage conversion gain of >4 dB. The buffered baseband outputs are capable of driving a 2 Vp-p differential signal into 200 Ω.The fully balanced design minimizes effects from second-order distortion. The leakage from the LO port to the RF port is 60 dBm.The ADL5387 operates off a single 4.75 V to 5.25 V supply. The supply current is adjustable with an external resistor from the BIAS pin to ground.The ADL5387 is fabricated using the Analog Devices, Inc. advanced silicon-germanium bipolar process and is available in a 24-lead exposed paddle LFCSP.APPLICATIONS QAM/QPSK RF/IF demodulators W-CDMA/CDMA/CDMA2000/GSM Microwave point-to-(multi)point radios Broadband wireless and WiMAX Broadband CATVs

50 dB GSM PA Controller Features: Complete RF detector/controller function >50 dB range at 0.9 GHz (-49 dBm to +2 dBm, re 50 Ω) Accurate scaling from 0.1 GHz to 2.5 GHz Temperature-stable linear-in-dB response Log slope of 23 mV/dB, intercept at -60 dBm at 0.9 GHz True integration function in control loop Low power: 20 mW at 2.7 V, 38 mW at 5 V Power-down to 10.8 µW

Low Phase Noise, Fast Settling PLL Frequency Synthesizer Features: New, fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 µs with phase settled by 20 µs 0.5° rms phase error at 2 GHz RF output Digitally programmable output phase RF input range up to 3.5 GHz 3-wire serial interface On-chip, low noise differential amplifier Phase noise figure of merit: –216 dBc/Hz Loop filter design possible using ADIsimPLL™ Qualified for automotive applications

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