The ADPA7009-2 is a gallium arsenide (GaAs), pseudomorphic high-electron-mobility transistor (pHEMT), monolithic microwave integrated circuit (MMIC), 0.5 W power amplifier with an integrated temperature-compensated, on-chip power detector that operates between 20 GHz and 54 GHz. The amplifier provides a gain of 17.5 dB, an output power for 1 dB compression (OP1dB) of 28 dBm, and a typical output third-order intercept (OIP3) of 34.5 dBm at 20 GHz to 35 GHz. The ADPA7009-2 requires 850 mA from a 5 V supply voltage (VDDx). The RF input and outputs are internally matched and DC-blocked for ease of integration into higher level assemblies. Most of the typically required external passive components for operation (AC coupling capacitors and power supply decoupling capacitors) are integrated, which facilitates a small, compact printed circuit board (PCB) footprint. The ADPA7009-2 is available in a 5.00 mm × 5.00 mm, 24-terminal chip array, small outline, no lead cavity [LGA_CAV] package.APPLICATIONS Military and space Test instrumentation

RF Amplifier LNA w/Failsafe Bypass , 700-1200 MHz

The AD8312 is a complete, low cost subsystem for the measurement of RF signals in the frequency range of 50 MHz to 3.5 GHz. It has a typical dynamic range of 45 dB and is intended for use in a wide variety of cellular handsets and other wireless devices. It provides a wider dynamic range and better accuracy than possible using discrete diode detectors. In particular, its temperature stability is excellent over the full operating range of −40°C to +85°C.Its high sensitivity allows measurement at low power levels, thus reducing the amount of power that needs to be coupled to the detector. It is essentially a voltage-responding device, with a typical signal range of 1.25 mV to 224 mV rms or −45 dBm to 0 dBm, referencing 50 Ω.For convenience, the signal is internally ac-coupled, using a 5 pF capacitor to a load of 3 kΩ in shunt with 1.3 pF. This high-pass coupling, with a corner at approximately 16 MHz, determines the lowest operating frequency. Therefore, the source may be dc grounded.The AD8312 output, VOUT, increases from close to ground to about 1.2 V because the input signal level increases from 1.25 mV to 224 mV. A capacitor may be connected between the VOUT and CFLT pins when it is desirable to increase the time interval over which averaging of the input waveform occurs.The AD8312 is available in a 6-ball, 1.0 mm × 1.5 mm, wafer-level chip scale package and consumes 4.2 mA from a 2.7 V to 5.5 V supply.Applications Cellular handsets (GSM, CDMA, WCDMA) RSSI and TSSI for wireless terminal devices Transmitter power measurement

The AD8364 is a true rms, responding, dual-channel RF powermeasurement subsystem for the precise measurement and controlof signal power. The flexibility of the AD8364 allows communicationssystems, such as RF power amplifiers and radio transceiverAGC circuits, to be monitored and controlled with ease. Operatingon a single 5 V supply, each channel is fully specified for operationup to 2.7 GHz over a dynamic range of 60 dB. The AD8364provides accurately scaled, independent, rms outputs of both RFmeasurement channels. Difference output ports, which measurethe difference between the two channels, are also available. Theon-chip channel matching makes the rms channel differenceoutputs extremely stable with temperature and process variations.The device also includes a useful temperature sensor with anaccurately scaled voltage proportional to temperature, specifiedover the device operating temperature range. The AD8364 canbe used with input signals having rms values from −55 dBm to+5 dBm referred to 50 Ω and large crest factors with noaccuracy degradation. Integrated in the AD8364 are two matched AD8362 channels(see the AD8362 data sheet for more information) with improvedtemperature performance and reduced log conformance ripple.Enhancements include improved temperature performance andreduced log-conformance ripple compared to the AD8362. On-chipwide bandwidth output operational amplifiers are connectedto accom-modate flexible configurations that support manysystem solutions.The device can easily be configured to provide four rmsmeasurements simultaneously. Linear-in-dB rms measurementsare supplied at OUTA and OUTB, with conveniently scaledslopes of 50 mV/dB. The rms difference between OUTA andOUTB is available as differential or single-ended signals atOUTP and OUTN. An optional voltage applied to VLVLprovides a common mode reference level to offset OUTP andOUTN above ground.The AD8364 is supplied in a 32-lead, 5 mm × 5 mm LFCSP, forthe operating temperature of –40°C to +85°C.Applications Wireless infrastructure power amplifier linearization/control Antenna VSWR monitor Gain and power control and measurement Transmitter signal strength indication (TSSI) Dual-channel wireless infrastructure radios

The AD8364 is a true rms, responding, dual-channel RF powermeasurement subsystem for the precise measurement and controlof signal power. The flexibility of the AD8364 allows communicationssystems, such as RF power amplifiers and radio transceiverAGC circuits, to be monitored and controlled with ease. Operatingon a single 5 V supply, each channel is fully specified for operationup to 2.7 GHz over a dynamic range of 60 dB. The AD8364provides accurately scaled, independent, rms outputs of both RFmeasurement channels. Difference output ports, which measurethe difference between the two channels, are also available. Theon-chip channel matching makes the rms channel differenceoutputs extremely stable with temperature and process variations.The device also includes a useful temperature sensor with anaccurately scaled voltage proportional to temperature, specifiedover the device operating temperature range. The AD8364 canbe used with input signals having rms values from −55 dBm to+5 dBm referred to 50 Ω and large crest factors with noaccuracy degradation. Integrated in the AD8364 are two matched AD8362 channels(see the AD8362 data sheet for more information) with improvedtemperature performance and reduced log conformance ripple.Enhancements include improved temperature performance andreduced log-conformance ripple compared to the AD8362. On-chipwide bandwidth output operational amplifiers are connectedto accom-modate flexible configurations that support manysystem solutions.The device can easily be configured to provide four rmsmeasurements simultaneously. Linear-in-dB rms measurementsare supplied at OUTA and OUTB, with conveniently scaledslopes of 50 mV/dB. The rms difference between OUTA andOUTB is available as differential or single-ended signals atOUTP and OUTN. An optional voltage applied to VLVLprovides a common mode reference level to offset OUTP andOUTN above ground.The AD8364 is supplied in a 32-lead, 5 mm × 5 mm LFCSP, forthe operating temperature of –40°C to +85°C.Applications Wireless infrastructure power amplifier linearization/control Antenna VSWR monitor Gain and power control and measurement Transmitter signal strength indication (TSSI) Dual-channel wireless infrastructure radios

The ADF4002 frequency synthesizer is used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the device can be used as a standalone PFD and charge pump.The ADF4002-EP supports defense and aerospace applications (AQEC standard).

The ADF4002 frequency synthesizer is used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the device can be used as a standalone PFD and charge pump.The ADF4002-EP supports defense and aerospace applications (AQEC standard).

The ADF4002 frequency synthesizer is used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the device can be used as a standalone PFD and charge pump.The ADF4002-EP supports defense and aerospace applications (AQEC standard).

The ADF4002 frequency synthesizer is used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the device can be used as a standalone PFD and charge pump.The ADF4002-EP supports defense and aerospace applications (AQEC standard).

The ADF4153 is a fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). In addition, the 4-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase- locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO).A simple 3-wire interface controls all on-chip registers. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.Applications CATV equipment Base stations for mobile radio (GSM, PCS, DCS, WiMAX, SuperCell 3G, CDMA, W-CDMA) Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA) Wireless LANs, PMR Communications test equipment