The LTC5532 is an RF power detector for RF applications operating in the 300MHz to 7GHz range. A temperature compensated Schottky diode peak detector and buffer amplifier are combined in a small ThinSOT? or (2mm x 2mm) DFN package. The supply voltage range is optimized for operation from a single lithium-ion cell or 3x NiMH.The RF input voltage is peak detected using an on-chip Schottky diode. The detected voltage is buffered and supplied to the VOUT pin.The LTC5532 output buffer gain is set via external resistors. The initial starting voltage of 120mV ?35mV can be precisely adjusted using the VOS pin.The LTC5532 operates with RF input power levels from ?32dBm to 10dBmApplications 802.11a, 802.11b, 802.11g, 802.15 Multimode Mobile Phone Products Optical Data Links Wireless Data Modems Wireless and Cable Infrastructure RF Power Alarm Envelope Detector

The HMC1119 is a broadband, highly accurate, 7-bit digitalattenuator, operating from 0.1 GHz to 6.0 GHz with 31.5 dBattenuation control range in 0.25 dB steps.The HMC1119 is implemented in a silicon process, offeringvery fast settling time, low power consumption, and high ESDrobustness. The device features safe state transitions and isoptimized for excellent step accuracy and high linearity overfrequency and temperature range. The RF input and output areinternally matched to 50 ? and do not require any externalmatching components. The design is bidirectional; therefore,the RF input and output are interchangeable.The HMC1119 has an on-chip regulator that can support a widesupply operating range from 3.3 V to 5.0 V with no performancechange in electrical characteristics. The HMC1119 incorporates adriver that supports serial (3-wire) and parallel controls of theattenuator.The HMC1119 comes in a RoHS-compliant, compact, 4 mm ?4 mm LFCSP package.A fully populated evaluation board is available.Applications Cellular infrastructure Microwave radios and very small aperture terminals (VSATs) Test equipment and sensors IF and RF designs

UltraFast 7ns Response Time 15GHz RF Power Detector with Comparator Features: Temperature Compensated Schottky RF Peak Detector Wide Input Frequency Range: 600MHz to 15GHz† Wide Input Power Range: –24dBm to 16dBm 7ns Typical Response Time 75MHz Demodulation Bandwidth Programmable Gain Settings for Improved Sensitivity Adjustable Amplifier Output Offset Voltage High Speed Comparator with Latch Enable: 9ns Typical Response Time 16-Lead 3mm × 3mm QFN Package Temperature Range: –40°C to 125°C†Higher frequency operation is achievable with reduced performance. Consult the factory formore information.

The AD6684 is a 135 MHz bandwidth, quad intermediate frequency (IF) receiver. It consists of four 14-bit, 500 MSPS ADCs and various digital processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed to support communications applications. The analog full power bandwidth of the device is 1.4 GHz. The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD6684 is optimized for wide input bandwidth, excellent linearity, and low power in a small package. The analog inputs and clock signal input are differential. Each pair of ADC data outputs are internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6684 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution. Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution. With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications andsupports tunable real IF sampling, and zero IF or complex IF receive architectures. Operation of the AD6684 in the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles (the default mode is NSR at startup).In addition to the DDC blocks, the AD6684 has several functions that simplify the AGC function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Users can configure each pair of IF receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins. The AD6684 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using the 1.8 V capable, 3-wire SPI. The AD6684 is available in a Pb-free, 72-lead LFCSP and is specified over the −40°C to +105°C junction temperature range. Product Highlights Low power consumption per channel. JESD204B lane rate support up to 15 Gbps. Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, W-CDMA, GSM, LTE, LTE-A HFC digital reverse path receivers Digital predistortion observation paths General-purpose software radios

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