HBT Vector Modulator SMT, 700 - 1000 MHz Features: Continuous Phase Control: 360° Continuous Gain Control: 40 dB Low Output Noise Floor: -162 dBm/Hz High Input IP3: +34 dBm 16 Lead 3×3mm SMT Package: 9mm2

40W SPDT Failsafe Switch SMT, 0.1 - 2.1 GHz Features: High Input P0.1dB: +46 dBm Tx Low Insertion Loss: 0.4 dB High IIP3: +74 dBm Single Positive Control: 0/ +3V to 0/ +8V Failsafe Operation; Tx 'On' when Unpowered 2 × 2mm DFN SMT Package

40W SPDT Failsafe Switch SMT, 0.1 - 2.1 GHz Features: High Input P0.1dB: +46 dBm Tx Low Insertion Loss: 0.4 dB High IIP3: +74 dBm Single Positive Control: 0/ +3V to 0/ +8V Failsafe Operation; Tx 'On' when Unpowered 2 × 2mm DFN SMT Package

RF Mixer

RF Amplifier

The ADPA7009-2 is a gallium arsenide (GaAs), pseudomorphic high-electron-mobility transistor (pHEMT), monolithic microwave integrated circuit (MMIC), 0.5 W power amplifier with an integrated temperature-compensated, on-chip power detector that operates between 20 GHz and 54 GHz. The amplifier provides a gain of 17.5 dB, an output power for 1 dB compression (OP1dB) of 28 dBm, and a typical output third-order intercept (OIP3) of 34.5 dBm at 20 GHz to 35 GHz. The ADPA7009-2 requires 850 mA from a 5 V supply voltage (VDDx). The RF input and outputs are internally matched and DC-blocked for ease of integration into higher level assemblies. Most of the typically required external passive components for operation (AC coupling capacitors and power supply decoupling capacitors) are integrated, which facilitates a small, compact printed circuit board (PCB) footprint. The ADPA7009-2 is available in a 5.00 mm × 5.00 mm, 24-terminal chip array, small outline, no lead cavity [LGA_CAV] package.APPLICATIONS Military and space Test instrumentation

The AD6684 is a 135 MHz bandwidth, quad intermediate frequency (IF) receiver. It consists of four 14-bit, 500 MSPS ADCs and various digital processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed to support communications applications. The analog full power bandwidth of the device is 1.4 GHz. The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD6684 is optimized for wide input bandwidth, excellent linearity, and low power in a small package. The analog inputs and clock signal input are differential. Each pair of ADC data outputs are internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6684 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution. Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution. With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications andsupports tunable real IF sampling, and zero IF or complex IF receive architectures. Operation of the AD6684 in the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles (the default mode is NSR at startup).In addition to the DDC blocks, the AD6684 has several functions that simplify the AGC function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Users can configure each pair of IF receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins. The AD6684 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using the 1.8 V capable, 3-wire SPI. The AD6684 is available in a Pb-free, 72-lead LFCSP and is specified over the −40°C to +105°C junction temperature range. Product Highlights Low power consumption per channel. JESD204B lane rate support up to 15 Gbps. Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, W-CDMA, GSM, LTE, LTE-A HFC digital reverse path receivers Digital predistortion observation paths General-purpose software radios

The HMC1040LP3CE is a self-biased GaAs MMIC Low Noise Amplifier housed in a leadless 3x3 mm plastic surface mount package. The amplifier operates between 24 and 43.5 GHz, delivering 23 dB of small signal gain, 2.2 dB noise figure, and output IP3 of +22 dBm, while requiring only 70 mA from a +2.5 V supply. The P1dB output power of +12 dBm enables the LNA to function as a LO driver for many of Hittite’s balanced, I/Q and image reject mixers. The HMC1040LP 3CE features I/Os that are DC blocked and internally matched to 50 Ohms, and is ideal for high capacity microwave radios and VSAT applications.Applications Point-to-Point Radios Test Instrumentation SatCom Transponders & VSAT Industrial Sensors EW & ECM Subsystems

The HMC1040LP3CE is a self-biased GaAs MMIC Low Noise Amplifier housed in a leadless 3x3 mm plastic surface mount package. The amplifier operates between 24 and 43.5 GHz, delivering 23 dB of small signal gain, 2.2 dB noise figure, and output IP3 of +22 dBm, while requiring only 70 mA from a +2.5 V supply. The P1dB output power of +12 dBm enables the LNA to function as a LO driver for many of Hittite’s balanced, I/Q and image reject mixers. The HMC1040LP 3CE features I/Os that are DC blocked and internally matched to 50 Ohms, and is ideal for high capacity microwave radios and VSAT applications.Applications Point-to-Point Radios Test Instrumentation SatCom Transponders & VSAT Industrial Sensors EW & ECM Subsystems

The HMC1127 is a GaAs pHEMT MMIC Distributed Power Amplifier which operates between 2 and 50 GHz. The amplifier provides 14.5 dB of gain, 23 dBm output IP3 and 12.5 dBm of output power at 1 dB gain compression while requiring 80 mA from a +5V supply. The HMC1127 amplifier I/Os are internally matched to 50 Ω facilitating integration into Multi-Chip-Modules (MCMs). All data is taken with the chip connected via two 0.025 mm (1 mil) wire bonds of minimal length 0.31 mm (12 mils).APPLICATIONS Test Instrumentation Microwave Radio & VSAT Military & Space Telecom Infrastructure Fiber Optics