HBT Vector Modulator SMT, 700 - 1000 MHz Features: Continuous Phase Control: 360° Continuous Gain Control: 40 dB Low Output Noise Floor: -162 dBm/Hz High Input IP3: +34 dBm 16 Lead 3×3mm SMT Package: 9mm2

LNA with Failsafe Bypass Mode SMT, 1700 - 2200 MHz Features: Noise Figure: 1.4 dB Output IP3: +29 dBm Gain: 17 dB Failsafe Operation: Bypass is enabled when LNA is unpowered Single Supply: +3V or +5V 16 Lead 3x3mm SMT Package: 9mm²

GaAs, pHEMT, MMIC, 1 W, Power Amplifier with Power Detector, 37 GHz to 40 GHz Features: 32 dBm typical saturated output power (PSAT) at 18% power added efficiency (PAE) at 39 GHz P1dB compression output power: 31.5 dBm typical High output third-order intercept (IP3): 40 dBm typical High gain: 24 dB typical 50 Ω matched input/output Ceramic, 6 mm × 6 mm, high frequency, air cavity package

4T2R Direct RF Transmitter and Observation Receiver Features: Flexible reconfigurable radio common platform design Transmit/receive channel bandwidth up to 1.2 GHz/2.4 GHz (4T2R) RFDAC/RFADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RFCLK input option Versatile digital features Configurable digital up/down conversion (DDC and DUC) 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs, 2 independent 48-bit NCO per DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Auxiliary features Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins supporting different user configurations ADC clock driver with selectable divide ratios TDD power savings option and sharing ADCs SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes per each DAC and ADC JESD204B compatible with maximum 15.5 Gbps lane rate JESD204C compatible with maximum 24.75 Gbps lane rate Supports real or complex digital data (8-bit, 12-bit, 16-bit, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

400 MHz TO 4000 MHz Low Noise Amplifier Features: Operation from 400 MHz to 4000 MHz Noise figure of 0.8 dB at 900 MHz Requires few external components Integrated active bias control circuit Integrated dc blocking capacitors Adjustable bias for low power applications Single-supply operation from 3 V to 5 V Gain of 20.8 dB at 900 MHz OIP3 of 37.0 dBm at 900 MHz P1dB of 21.8 dBm at 900 MHz Small footprint LFCSP Pin-compatible version with 21.5 dB gain available

21.2 GHz to 23.6 GHz, Low Noise Amplifier Features: Frequency range: 21.2 GHz to 23.6 GHz Typical gain of >22.5 dB Low noise input Noise figure 3.3 dB typical at 21.2 GHz 3.4 dB typical at 23.6 GHz High linearity input ≥1.0 dBm typical input third-order intercept (IIP3) −8 dBm input 1 dB compression point (P1dB) at 23.6 GHz Matched 50 Ω single-ended input Matched 100 Ω differential outputs 8-lead, 2.00 mm × 2.00 mm LFCSP microwave packaging

10 GHz to 40 GHz, 1:4 Channel, 4 Frequency Multiplier/Filter Features: 4 input frequency multiplier with programmable harmonic filter Quad Differential Output PAs with independent Enable Control Input Frequency Range: 2.5 GHz to 10 GHz Output Frequency Range: 10 GHz to 40 GHz Input power: 20 dBm (50 ) Output power: 5 dBm differential (100 ) Harmonic rejection: 20 dBc to 40 dBc at all frequencies 3-Wire or 4-Wire SPI Control of all functions On-Chip Programmable State Machines for fast multiplier/filter and transmitter switching and control On-chip temperature sensor, output power detectors, and ADC DC power: 450 mW (2.5 V supply) 6 mm 6 mm, 40-terminal LGA package

Phase Detector / PLL Frequency Synthesizer Features: 400 MHz bandwidth 2.7 to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode 104  MHz phase detectorADF4002-EP supports defense and aerospace applications (AQEC standard) Download ADF4002-EP data sheet (pdf) Military temperature range: −55°C to +125°C Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/11607 DSCC Drawing Number

RF Amplifier lo Noise amp Chip, 23 - 32 GHz

RF Mixer DBL-BAL mix SMT 9 - 15 GHz