EVALUATION PCB ASSEMBLY

Medium pow amp SMT 6 - 18 GHz

The ADuCRF101 is a fully integrated, data acquisition solution that is designed for low power, wireless applications. It features a 12-bit analog-to-digital converter (ADC), a low power ARM Cortex™-M3 processor, a 862 MHz to 928 MHz and 431 MHz to 464 MHz RF transceiver, and Flash®/EE memory. The ADuCRF101 is packaged in a 9 mm × 9 mm LFCSP.The data acquisition section consists of a 12-bit SAR ADC. The six inputs can be configured in single-ended or differential mode. When configured in single-ended mode, they can be used for ratiometric measurements on sensors that are powered, when required, from the internal low dropout regulator (LDO). An internal battery monitor channel and an on-chip temperature sensor are also available.This wireless data acquisition system is designed to operate in battery-powered applications where low power is critical. The device can be configured in normal operating mode or different low power modes under direct program control. In flexi mode, any peripheral can wake up the device and operate it. In hibernate mode, the internal wake-up timer remains active. In shutdown mode, only an external interrupt can wake up the device.The ADuCRF101 integrates a low power ARM Cortex-M3 processor. It is a 32-bit RISC machine, offering up to 1.25 DMIPS peak performance. The ARM Cortex-M3 processor also has a flexible 14-channel direct memory access (DMA) controller that supports communication peripherals, serial peripheral interface (SPI), UART, and I2C. Also provided on chip are 128 kB of nonvolatile Flash/EE memory and 16 kB of SRAM.A 16 MHz on-chip oscillator generates the system clock. This clock can be internally divided for the processor to operate at a lower frequency, thus saving power. A low power, internal 32 kHz oscillator is available and can be used to clock the four timers, as follows: two general-purpose timers, a wake-up timer, and a system watchdog timer.A range of communication peripherals can be configured, as required, in a specific application. These peripherals include UART, I2C, SPI, GPIO ports, PWM, and RF transceivers.The RF transceiver communicates in the 862 MHz to 928 MHz and 431 MHz to 464 MHz frequency bands using multiple configurations.On-chip factory firmware supports in-circuit serial download via the UART, and nonintrusive emulation and program download are also supported via the serial wire interface. These features are incorporated into a low cost development system supporting this precision analog microcontroller family.The ADuCRF101 operates from 2.2 V to 3.6 V and is specified over an industrial temperature range of −40°C to +85°C. It is available in a 64-lead LFCSP packageApplications Battery powered wireless sensor Medical telemetry systems Industrial and home automation Asset tracking Security systems (access systems) Health and fitness applications  

DIGITAL ATTENUATOR, 0-6GHZ, QFN-EP;

The ADL8104 is a gallium arsenide (GaAs), monolithic microwave integrated circuit (MMIC), pseudomorphic high electron mobility transistor (pHEMT), low noise, wideband, high linearity amplifier that operates from 0.4 GHz to 7.5 GHz.The ADL8104 provides a typical gain of 15 dB at 0.6 GHz to 6 GHz, a 3.5 dB typical noise figure at 0.4 GHz to 6 GHz, a 20 dBm typical output power for 1 dB compression (OP1dB) at 0.6 GHz to 6 GHz, and a typical output third-order intercept (OIP3) of 32 dBm at 0.6 GHz to 6 GHz, requiring only 150 mA from a 5 V drain supply voltage. The low noise amplifier has a high output second-order intercept (OIP2) of 52 dBm typical at 0.6 GHz to 6 GHz, making the ADL8104 suitable for military and test instrumentation applications.The ADL8104 also features inputs and outputs that are internally matched to 50 ?. The RFIN and RFOUT pins are internally ac-coupled and the bias inductor is also integrated, making the ADL8104 ideal for surface-mounted technology (SMT)-based, high density applications.The ADL8104 is housed in an RoHS-compliant, 3 mm ? 3 mm, 16-lead LFCSP.APPLICATIONSTest instrumentationMilitary communications

The LTC5566 dual programmable gain downconverting mixer is ideal for diversity and MIMO receivers that require precise gain setting. Each channel incorporates an active mixer and a digital IF VGA with 15.5dB gain control range. The IF gain of each channel is programmed in 0.5dB steps through the SPI.Programmable RF input tuning via the SPI or parallel control lines makes the device attractive for wideband radio applications. Furthermore, a reduced power mode is available, programmed through the SPI.Integrated RF transformers provide single-ended 50? inputs. The differential LO input is designed for single-ended or differential drive. The differential IF output simplifies the interface to differential IF filters and amplifiers. The mixers are optimized for use up to 5GHz but may be used up to 6GHz with degraded performance.Applications 4G and 5G MIMO Receivers Diversity Receivers Distributed Antenna Systems (DAS) Network Test/Monitoring Equipment Software-Defined Radios

The ADL5246 is a high performance, low noise variable gain amplifier (VGA) optimized for multistandard base station receivers and point to point receive (Rx) and transmit (Tx) applications. The low noise figure and excellent linearity performance allow the device to be used in a variety of applications.The device consists of a low noise amplifier, a high linearity VGA, and a ½ W output driver stage. The variable attenuator networks are optimized to provide high linearity performance over the 45 dB gain control range. Gain is set using a unipolar control voltage from 0 V to 3.3 V. The output stage of the ADL5246 is an externally tuned ½ W driver amplifier, which allows the device to be optimized anywhere between the 0.6 GHzto 3 GHz range, with an average tuning bandwidth of 200 MHz wide. An external filter can be used between the VGA and the final driver amplifier. The ADL5246 can be biased between 3.3 V and 5 V to tradeoff between performance and power consumption.The ADL5246 is fabricated on an advanced GaAs process. The device is available in a 32-lead, RoHS-compliant, 5 mm × 5 mm LFCSP and thermally rated to operate over the −40°C to +105°C temperature range.APPLICATIONS Multistandard radio receivers Point to point Rx and Tx Instrumentation Military and aerospace

The HMC618ALP3E is a GaAs pHEMT MMIC Low Noise Amplifier that is ideal for Cellular/3G and LTE/WiMAX/4G basestation front-end receivers operating between 1.2 - 2.2 GHz. The amplifier has been optimized to provide 0.75 dB noise figure, 19 dB gain and +36 dBm output IP3 from a single supply of +5V. Input and output return losses are excellent and the LNA requires minimal external matching and bias decoupling components. The HMC618ALP3E shares the same package and pinout with the HMC617LP3E 0.55 - 1.2 GHz LNA. The HMC618ALP3E can be biased with +3V to +5V and features an externally adjustable supply current which allows the designer to tailor the linearity performance of the LNA for each application. The HMC618ALP3E offers improved noise figure versus the previously released HMC375LP3(E) and the HMC382LP3(E).Applications Cellular/3G and LTE/WiMAX/4G BTS & Infrastructure Repeaters and Femto Cells Public Safety Radio

RF Amplifier dig Variable-Gain

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment