HMC750 is a limiting amplifier designed to support data transmission rates up to 12.5 Gbps. The amplifier can operate over a wide range of input voltage levels and provides constant-level differential output swing. HMC750 also features an output level control pin, VC1, which allows for loss compensation or for signal level optimization. Differential output signal swing can be adjustable up to 880 mVp-p. Input signals higher than 3 mVp-p can be amplified to saturated 880 mVp-p differential signal.All single-ended input signals to the HMC750 are terminated with 50 ohms to +5V on-chip, and may be either AC or DC coupled. The outputs of the HMC750 may be operated either differentially or single-ended. Outputs can be connected directly to a 50 ohm terminated system referenced to +5V, while DC blocking capacitors may be used if the terminating system is 50 ??to a non +5V voltage. The HMC750 operates from a single +5V DC supply and is available in a plastic RoHS compliant 4?4 mm SMT package.APPLICATIONS OC-192 Receivers 10 Gbps Ethernet Receivers 10 Gbps Fiber Channel Receivers Broadband Test & Measurement

The HMC748 is a 2:1 Selector designed to support data transmission rates of up to 13 Gbps, and selector port operation of up to 13 GHz. The selector routes one of the two single-ended inputs to the differential output upon assertion of the proper select port. The HMC748 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All single-ended input signals to the HMC748 are terminated with 50 ohms to VCC?on-chip, and may be either AC or DC coupled. The outputs of the HMC748 may be operated either differentially or single-ended. Inputs or outputs can be connected directly to a 50 ohm to VCC terminated system, while DC blocking capacitors may be used if the terminating system is 50 ohms to ground. The HMC748 operates from a single +3.3V DC supply and is housed in a ceramic RoHS compliant 3x3 mm SMT package.APPLICATIONS 2:1 Multiplexer up to 13 Gbps RF ATE Applications Broadband Test & Measurement Serial Data Transmission up to 13 Gbps Redundant Path Switching Built-in Test

The HMC959LC3 is a Divide-by-4 with Reset designed to support clock frequencies as high as 26 GHz. During normal operation, with the reset pin not asserted, the output toggles from its prior state on the positive edge of the clock. This results in a divide-by-four function of the clock input. Asserting the reset pin forces the Q output low regardless of the clock edge state (asynchronous reset assertion). Reversing the clock inputs allows for negative-edge triggered applications. The HMC959LC3 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All input signals to the HMC959LC3 are terminated with 50 ? to ground on-chip, and may be either AC or DC coupled. Outputs can be connected directly to a 50 ? terminated system, while DC blocking capacitors may be used if the terminating system is 50 ? to a non-ground DC voltage. The HMC959LC3 operates from a single -3.3 V DC supply and is available in a ceramic RoHS-compliant 3?3 mm SMT package.APPLICATIONS High Speed Frequency Divider?(up to 26 GHz) Broadband Test & Measurement Clock Synthesis Phase Locked Loops

The HMC752LC4 is a GaAs MMIC Low Noise WidebandAmplifier housed in a leadless 4x4 mm ceramicsurface mount package. The amplifier operates between24 and 28 GHz, providing up to 25 dB of smallsignal gain, 2.5 dB noise figure, and output IP3 of+26 dBm, while requiring only 70 mA from a +3V supply.The P1dB output power of up to +13 dBm enablesthe LNA to function as a LO driver for balanced, I/Qor image reject mixers. The HMC752LC4 also featuresI/Os that are DC blocked and internally matched to50 Ohms, making it ideal for high capacity microwaveradios or VSAT applications.Applications Point-to-Point Radios Point-to-Multi-Point Radios Military & Space Test Instrumentation

The HMC960LP4E is a digitally programmable dual channel variable gain amplifier. It supports discrete gain steps from 0 to 40 dB in precise 0.5 dB steps. It features a glitch free architecture to provide exceptionally smooth gain transitions. The device has matched gain paths which provide excellent quadrature balance over a wide signal bandwidth.The HMC960LP4E provides an SPI programmable input impedance of 100? differential or 400? differential (default).Externally controlled common mode output feature enables the HMC960LP4E to provide a flexible output interface to other parts in the signal path. Gain can be controlled via either a parallel interface (GC[6:0]) or via the read/write serial port (SPI).Housed in a compact 4x4mm (LP4) SMT QFN package, the HMC960LP4E requires minimal external components and provides a low cost alternative to more complicated switched amplifier architectures.Applications Baseband I/Q Transceivers Direct Conversion &?Low IF Transceivers Diversity Receivers ADC Drivers Adaptive Gain Control

The HMC966LP4E is a compact GaAs MMIC I/Q downconverter in a leadless RoHS compliant SM T package. This device provides a small signal conversion gain of 12 dB with a noise figure of 2.5 dB and 40 dBc of image rejection across the frequency band. The HMC966LP4E utilizes an LNA followed by an image reject mixer which is driven by an active x2 multiplier. The image reject mixer eliminates the need for a filter following the LNA, and removes thermal noise at the image frequency. I and Q mixer outputs are provided and an external 90? hybrid is needed to select the required sideband. The HMC966LP4E is a much smaller alternative to hybrid style image reject mixer downconverter assemblies, and is compatible with surface mount manufacturing techniques.Applications Point-to-Point &?Point-to-Multi-Point Radio Military Radar, EW & ELINT Satellite Communications

The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Applications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD6688-3000EBZ supports the AD6688-3000, a 14-bit, 3GSPS dual analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed support direct RF sampling analog signals of up to 5 GHz. The 3 dB bandwidth of the ADC input is greater than 9 GHz. The AD6688 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS7-V2EBZ data capture card, allowing users to download captured data for analysis. The device control and subsequent data analyses can now be done using the ACE software package.

The AD8333 is a dual-phase shifter and I/Q demodulator that enables coherent summing and phase alignment of multiple analog data channels. It is the first solid-state device suitable forbeamformer circuits, such as those used in high performance medical ultrasound equipment featuring CW Doppler. The RF inputs interface directly with the outputs of the dual-channel, low noise preamplifiers included in the?AD8332.A divide-by-4 circuit generates the internal 0? and 90? phases of the local oscillator (LO) that drive the mixers of a pair of matched I/Q demodulators.The AD8333 can be applied as a major element in analog beamformer circuits in medical ultrasound equipment.The AD8333 features an asynchronous reset pin. When used in arrays, the reset pin sets all the LO dividers in the same state. Sixteen discrete phase rotations in 22.5? increments can be selected independently for each channel. For example, if Channel 1 is used as a reference and the RF signal applied to Channel 2 has an I/Q phase lead of 45?, Channel 2 can be phase aligned with Channel 1 by choosing the correct code.Phase shift is defined by the output of one channel relative to another. For example, if the code of Channel 1 is adjusted to 0000 and that of Channel 2 to 0001 and the same signal is applied to both RF inputs, the output of Channel 2 leads that of Channel 1 by 22.5?.The I and Q outputs are provided as currents to facilitate summation. The summed current outputs are converted to voltages by a high dynamic-range, current-to-voltage (I-V) converter, such as the AD8021, configured as a transimpedance amplifier. The resultant signal is then applied to a high resolution ADC, such as the AD7665 (16 bit/570 kSPS).The two I/Q demodulators can be used independently in other nonbeamforming applications. In that case, a transimpedance amplifier is needed for each of the I and Q outputs, four in total for the dual I/Q demodulator.The dynamic range is 159 dB/Hz at each I and Q output, but the following transimpedance amplifier is an important element in maintaining the overall dynamic range, and attention needs to be paid to optimal component selection and design.The AD8333 is available in a 32-lead LFCSP (5 mm ? 5 mm) package for the industrial temperature range of ?40?C to +85?C.Applications Medical imaging (CW ultrasound beamforming) Phased array systems (radar and adaptive antennas) Communication receivers

The AD8349 is high performance quadrature modulator design for use as a single stage up-converter within wireless infrastructure equipment.The AD8349 provides a high output power and very low noise floor supporting a significant improvement in the output signal range. Additionally the excellent phase and amplitude balance accuracy support a higher sideband suppression specification enabling higher order / capacity QAM modulated radios.The AD8349 has been tested for use over the common Cellular bands (900 MHz, 1.9 GHz, 2.1 GHz) meeting the needs as specified by the CDMA/GSM Edge/W-CDMA standards.The AD8349 is supplied in 16-lead Thin Shrunk Small Outline (TSSOP) package, and fully specified over -40?C to 85?C temperature range.APPLICATIONS Cellular/PCS communication systems infrastructure WCDMA/CDMA2000/PCS/GSM/EDGE Wireless LAN/wireless local loop LMDS/broadband wireless access systemsAVAILABILITYSamples (part number AD8349ARE) and an evaluation board (part number AD8349-EVAL) are available. Other Modulator / Demodulator ProductsAD8345 - 250 - 1000 MHz RF / IF Quadrature ModulatorAD8346 - 2.5 GHz Direct Conversion Quadrature ModulatorAD8347 - 800 MHz to 2.7 GHz RF / IF Quadrature DemodulatorAD8348 - 50 - 1000 MHz RF / IF Quadrature Demodulator