RF Amplifier lo Noise amp SMT, 350 - 550 MHz

Low Noise Amplifier Chip, 7.0 - 13.5 GHz Features: Noise Figure: 1.8 dB Gain: 17 dB OIP3: 24 dBm Single Supply: +3V @ 51 mA 50 Ohm Matched Input/Output Small Size: 1.96 x 0.98 x 0.10 mm

HMC5927LS6 - Amplifier Evaluation Board

GaAs InGaP HBT MMIC Ultra Low Phase Noise, Distributed Amplifier, 2 - 18 GHz Features: Ultra Low Phase Noise: -160 dBc/Hz @ 10 kHz P1dB Output Power: +15 dBm Gain: 14 dB Output IP3: +27 dBm Supply Voltage: +5V @ 64 mA 50 Ω Matched Input/Output Die Size: 2.80 x 1.73 x 0.1 mm

Fractional-N PLL with Integrated VCO SMT, 1815 - 2010 MHz Features: RF Bandwidth: 1815 - 2010 MHz Fractional or Integer Modes 19-Bit Prescaler Ultra Low Phase Noise -110 dBc/Hz in Band Typ. Figure of Merit (FOM) -227 dBc Integer 24-Bit Step Size, 3 Hz Resolution Typ. 200 MHz, 14-bit Reference Path Input Cycle Slip Prevention 40 Lead 6x6mm SMT Package: 36mm²

The AD8364 is a true rms, responding, dual-channel RF powermeasurement subsystem for the precise measurement and controlof signal power. The flexibility of the AD8364 allows communicationssystems, such as RF power amplifiers and radio transceiverAGC circuits, to be monitored and controlled with ease. Operatingon a single 5 V supply, each channel is fully specified for operationup to 2.7 GHz over a dynamic range of 60 dB. The AD8364provides accurately scaled, independent, rms outputs of both RFmeasurement channels. Difference output ports, which measurethe difference between the two channels, are also available. Theon-chip channel matching makes the rms channel differenceoutputs extremely stable with temperature and process variations.The device also includes a useful temperature sensor with anaccurately scaled voltage proportional to temperature, specifiedover the device operating temperature range. The AD8364 canbe used with input signals having rms values from −55 dBm to+5 dBm referred to 50 Ω and large crest factors with noaccuracy degradation. Integrated in the AD8364 are two matched AD8362 channels(see the AD8362 data sheet for more information) with improvedtemperature performance and reduced log conformance ripple.Enhancements include improved temperature performance andreduced log-conformance ripple compared to the AD8362. On-chipwide bandwidth output operational amplifiers are connectedto accom-modate flexible configurations that support manysystem solutions.The device can easily be configured to provide four rmsmeasurements simultaneously. Linear-in-dB rms measurementsare supplied at OUTA and OUTB, with conveniently scaledslopes of 50 mV/dB. The rms difference between OUTA andOUTB is available as differential or single-ended signals atOUTP and OUTN. An optional voltage applied to VLVLprovides a common mode reference level to offset OUTP andOUTN above ground.The AD8364 is supplied in a 32-lead, 5 mm × 5 mm LFCSP, forthe operating temperature of –40°C to +85°C.Applications Wireless infrastructure power amplifier linearization/control Antenna VSWR monitor Gain and power control and measurement Transmitter signal strength indication (TSSI) Dual-channel wireless infrastructure radios

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

Analog Variable Gain Amplifier SMT, 5 - 12 GHz Features: Wide Gain Control Range: 22 dB Single Control Voltage: -1 to -4.5V Output IP3 @ Max Gain: +34 dBm Output P1dB: +22 dBm No External Matching 24 Lead 4x4 mm SMT Package: 16 mm²

2 GHz Ultralow Distortion Differential RF/IF Amplifier Features: −3 dB bandwidth of 2.2 GHz (AV = +10 dB) Single resistor gain adjust: 3 dB ≤ AV ≤ 25 dB Single resistor and capacitor distortion adjust Input resistance: 3 kΩ, independent of gain (AV) Differential or single-ended input to differential output Low noise input stage: 2.7 nV/√Hz RTI at AV = 10 dB Low broadband distortion 10 MHz: −86 dBc HD2, −82 dBc HD3 70 MHz: −84 dBc HD2, −82 dBc HD3 190 MHz: −81 dBc HD2, −87 dBc HD3 OIP3 of 41 dBm at 150 MHz Slew rate: 8 V/ns Fast settling and overdrive recovery of <2 ns Single-supply operation: 3 V to 5.5 V Low power dissipation: 37 mA typical at 5 V Power-down capability: 5 mA at 5 V Fabricated using the high speed XFCB3 SiGe process

1.6GHz to 2.7GHz High Dynamic Range Downconverting Mixer Features: Conversion Gain: 8dB at 2.4GHz IIP3: 26.8dBm at 2.4GHz Noise Figure: 9.9dB at 2.4GHz 17.3dB NF Under +5dBm Blocking High Input P1dB 3.3V Supply, 660mW Power Consumption Shutdown Pin 50Ω Single-Ended RF and LO Inputs LO Inputs 50Ω Matched when Shutdown High Isolation LO Switch 0dBm LO Drive Level High LO-RF and LO-IF Isolation Small Solution Size 20-Lead (5mm × 5mm) QFN package