The AD8319 is a demodulating logarithmic amplifier, capable of accurately converting an RF input signal to a corresponding decibel-scaled output. It employs the progressive compression technique over a cascaded amplifier chain, each stage of which is equipped with a detector cell. The device can be used in either measurement or controller modes. The AD8319 maintains accurate log conformance for signals of 1 MHz to 8 GHz and provides useful operation to 10 GHz. The input dynamic range is typically 40 dB (re: 50 ?) with error less than ?1 dB. The AD8319 has 8 ns/10 ns response time (fall time/rise time) that enables RF burst detection to a pulse rate of beyond 50 MHz. The device provides unprecedented logarithmic intercept stability vs. ambient temperature conditions. A supply of 3.0 V to 5.5 V is required to power the device. Current consumption is typically 22 mA, and it decreases to 200 ?A when the device is disabled.?The AD8319 can be configured to provide a control voltage to a power amplifier or a measurement output from the VOUT pin. Because the output can be used for controller applications, special attention was paid to minimize wideband noise. In this mode, the setpoint control voltage is applied to the VSET pin.The feedback loop through an RF amplifier is closed via VOUT, the output of which regulates the amplifier?s output to a magnitude corresponding to VSET. The AD8319 provides 0 V to (VPOS ? 0.1 V) output capability at the VOUT pin, suitable for controller applications. As a measurement device, VOUT is externally connected to VSET to produce an output voltage, VOUT, that is a decreasing linear-in-dB function of the RF input signal amplitude.The logarithmic slope is ?22 mV/dB, determined by the VSET interface. The intercept is 15 dBm (re: 50 ?, CW input) using the INHI input. These parameters are very stable against supply and temperature variations.The AD8319 is fabricated on a SiGe bipolar IC process and is available in a 2 mm ? 3 mm, 8-lead LFCSP_VD for an operating temperature range of ?40?C to +85?C.ApplicationsRF transmitter PA setpoint controls and level monitoring Power monitoring in radiolink transmitters RSSI measurement in base stations, WLANs, WiMAX, and radars

The HMC472ALP4E are broadband 6-bit GaAs IC digital attenuators in low cost leadless surface mount packages. This single positive control line per bit digital attenuator incorporates off chip AC ground capacitors for near DC operation, making it suitable for a wide variety of RF and IF applications. Covering DC to 3.8 GHz, the insertion loss is less than 2.0 dB typical. The attenuator bit values are 0.5 (LSB), 1, 2, 4, 8, and 16 dB for a total attenuation of 31.5 dB. Attenuation accuracy is excellent at ? 0.25 dB typical step error with an IIP3 of +54 dBm. Six TTL/CMOS control inputs are used to select each attenuation state. A single Vdd bias of +5V is required.APPLICATIONSThe HMC472ALP4E is ideal for: 3G Infrastructure & access points? Cellular/3G, LTE & UMB WiMAX, WiBN & Fixed Wireless? Test Equipment and Sensors GSM, WCDMA & TD-SCDMA

POWER AMP 22DB 24-27GHZ 5V LCC-24; Frequency Min:24GHz; Frequency Max:27GHz; Gain:22dB; Noise Figure Typ:-; RF IC Case Style:LCC; No. of Pins:24Pins; Supply Voltage Min:-; Supply Voltage Max:5V; Operating Temperature Min:-40 C

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

Amplifiers ;RoHS Compliant: Yes

Amplifier Power 5.5-8.5GHz 5W ;RoHS Compliant: Yes

Die Sales- Sample Pack

EVALUATION PCB ASSEMBLY

HMC6147ALC5A EVALUATION BOARD

EVALUATION PCB ASSEMBLY