100MHz to 40GHz Linear-in-dB RMS Power Detector with 35dB Dynamic Range Features: Ultra Wide Matched Input Frequency Range: 100MHz to 40GHz 35dB Linear Dynamic Range (< ±1dB Error) 29mV/dB Logarithmic Slope ±1dB Flat Response from 200MHz to 30GHz Accurate RMS Power Measurement of High Crest Factors (Up to 12dB) Modulated Waveforms Low Power Shutdown Mode Low Supply Current: 30mA at 3.3V (Typical) Small 2mm × 2mm Plastic DFN8 Package I-Grade: –40°C to 105°C Rated H-Grade: –40°C to 125°C Rated with Guaranteed Log-Slope and Log-Intercept ESD Rating: 3500V HBM, 1500V CDM

Integrated Dual RF Receiver Features: Dual receivers Maximum Receiver BW: 200 MHz Fully integrated, fractional-N, RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuneable range: 75 MHz to 6000 MHz

40MHz to 10GHz RMS Power Detector with 57dB Dynamic Range Features: Frequency Range: 40MHz to 10GHz Linear Dynamic Range: Up to 57dB Accurate RMS Power Measurement of High Crest Factor Modulated Waveforms Exceptional Accuracy Over Temperature: ±0.5dB (Typ) Low Linearity Error within Dynamic Range Single-Ended or Differential RF Inputs Fast Response Time: 90ns Rise Time Low Supply Current: 41.6mA at 3.3V (Typ) Small 3mm × 3mm DFN10 AEC-Q100 Qualified for Automotive Applications

Matched Dual-Channel 6GHz RMS Power Detector Features: Frequency Range: 40MHz to 6GHz Linear Dynamic Range: Up to 60dB ±0.5dB (Typ) Accuracy Over Temperature 40dB Channel-to-Channel Isolation at 2GHz Even with Single-Ended RF Inputs Matched Dual-Channel Outputs: <1.25dB (Typ) Single-Ended RF Inputs—No Transformer Required Accurate RMS Power Measurement of High Crest Factor Modulated Waveforms Difference Output Provides VSWR Measurement Fast Envelope Detector Outputs Fast Response Time: 140ns Rise Time Small 4mm × 4mm QFN24 Package 

GaAs MMIC I/Q Downconverter, 17 - 24 GHz Features: Conversion Gain: 12 dB Image Rejection: 30 dB 2 LO to RF Isolation: 45 dB Noise Figure: 3 dB Input IP3: 0 dBm 32 Lead 5x5mm SMT Package: 25mm2

The LTC6430-20 is a differential gain block amplifier designed to drive high resolution, high speed ADCs with excellent linearity beyond 1000MHz and with low associated output noise. The LTC6430-20 operates from a single 5V power supply and consumes only 850mW.In its differential configuration, the LTC6430-20 can directly drive the differential inputs of an ADC. Using 1:2 baluns, the device makes an excellent 50Ω wideband balanced amplifier. While using 1:1.33 baluns, the device creates a high fidelity 40MHz to 1000MHz 75Ω CATV amplifier.The LTC6430-20 is designed for ease of use, requiring a minimum of support components. The device is internally matched to 100Ω differential source/load impedance. On-chip bias and temperature compensation ensure consistent performance over environmental changes.The LTC6430-20 uses a high performance SiGe BiCMOS process for excellent repeatability compared with similar GaAs amplifiers. All A-grade LTC6430-20 devices are tested and guaranteed for OIP3 at 380MHz. The LTC6430-20 is housed in a 4mm × 4mm, 24-lead, QFN package with an exposed pad for thermal management and low inductance. A single-ended 50Ω IF gain block with similar performance is also available, see the related LTC6431-20.Applications Differential ADC Driver Differential IF Amplifier OFDM Signal Chain Amplifier 50Ω Balanced IF Amplifier 75Ω CATV Amplifier 700MHz to 800MHz LTE Amplifier Low Phase Noise Clock or LO Amplifier

The ADF5904 is a 4-channel, 24 GHz, receiver downconverter.Each channel contains a single-ended RF input with an on-chipbalun followed by a differential low noise amplifier (LNA) and adownconverter mixer with differential output buffers. The RFLO path also has an on-chip balun.Control of the on-chip registers is through a simple 3-wireinterface.The ADF5904 comes in a compact 32-lead, 5 mm × 5 mmLFCSP package.Applications Automotive radars Industrial radars Microwave (µW) radar sensors

The HMC424AG16 is a broadband 6-bit GaAs IC digital attenuator in a 16 lead glass/metal (hermetic) surface mount package. Covering DC to 3 GHz, the insertion loss is less than 3 dB typical. The attenuator bit values are 0.5 (LSB), 1, 2, 4, 8, and 16 dB for a total attenuation of 31.5 dB. Attenuation accuracy is excellent at ±0.5 dB typical step error with an IIP3 of +34 dBm. Six control voltage inputs, toggled between 0 and -5V, are used to select each attenuation state at less than 70 μA each. A single Vee bias of -5V allows operation at frequencies down to DC.Applications Telecom Infrastructure Military Radios, Radar & ECM Space Applications Test Instrumentation

The SC1894 is the Scintera® 3rd generation of RF PA linearizers(RFPAL™) that provide improved correction and functionality over the previous generations. The SC1894 is a fully adaptive, RFin/RFout predistortion linearization solution optimized for a wide range of amplifiers, power levels, and communication protocols. The SC1894 uses the PA output and input signals to adaptively generate an optimized correction function in order to minimize the PA’s self-generated distortion and impairments. Using RF-domain analog signal processing enables the SC1894 to operate over wide-signal bandwidths and consume very low power. The SC1894 goes beyond linearization and provides accurate RF power measurement of RFIN and RFFB. Design support features including spectral monitoring and ACLR alarm are also available. These optional design support are accessed through the SC1894’s serial peripheral interface (SPI) bus.Evaluation kits are available for evaluating the performance of the SC1894. See the SC1894 data sheet for the frequency variants. See the ordering tab for EV Kit options. NOTE: The SC1894EVKit requires the use of the SC-USB-SPI-PICO board to connect the SC1894EVKit into a computer.Note: All SCxx parts are RoHS. An appended “E” at the end of the part number indicates 7” Tape and Reel. No appended letter or a “K” at the end of the part number indicates bulk.How to Fix a Corrupted EEPROM on an SC1905EVKIT or SC1894EVKIT SC2200 and SC1894 RF Power Amplifier Linearizers RF Power Amplifier Linearization Technology ApplicationsBroadcast Infrastructure (SC1894A-00C13)Cellular Infrastructure (SC1894A-00C13)Microwave Backhaul (SC1894A-00M13)Wide Range of PAs and Output Power

The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k × 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS port after being stored in the integrated FIFO memory. It is optimized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. All necessary functions, including the sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution.The on-chip FIFO allows small snapshots of time to be captured via the ADC and read back at a lower rate. This reduces the constraints of signal processing by transferring the captured data at an arbitrary time and at a much lower sample rate. The FIFO can be operated in several user-programmable modes. In the single capture mode, the ADC data is captured when signaled via the SPI port or the use of the external FILL± pins. In the continuous capture mode, the data is loaded continuously into the FIFO and the FILL± pins are used to stop this operation.The data stored in the FIFO can be read back based on several user-selectable output modes. The DUMP pin can be asserted to output the FIFO data. The data stored in the FIFO can be accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit DDR LVDS interface. The maximum output throughput supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR LVDS mode and is internally limited to 1/8th of the maximum input sample rate. This corresponds to the maximum output data rate of 62.5 MHz at an input clock rate of 500 MSPS.The ADC requires a 1.9 V analog voltage supply and a differential clock for full performance operation. Output format options include twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced SiGe BiCMOS process, the device is available in a 56-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C). This product is protected by a U.S. patent.APPLICATIONS Wireless and wired broadband communications Communications test equipment Power amplifier linearizationPRODUCT HIGHLIGHTS High Performance ADC Core. Maintains 65.8 dBFS SNR at 500 MSPS with a 250 MHz input. Low Power. Consumes only 695 mW at 500 MSPS. Ease of Use. On-chip 16k FIFO allows the user to target the high performance ADC to the time period of interest and reduce the constraints of processing the data by transferring it at an arbitrary time and a lower sample rate. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.9 V supply simplifies system power supply design. Serial Port Control. Standard serial port interface supports configuration of the device and customization for the user’s needs. 1.9 V or 3.3 V SPI and Serial Data Port Operation.