The ADRF5250 is a general-purpose, single-pole, five-throw (SP5T), nonreflective switch manufactured using a silicon process. The ADRF5250 is available in a 4 mm ? 4 mm, 24-lead lead frame chip scale package (LFCSP) and provides high isolation and low insertion loss from 100 MHz to 6 GHz.The ADRF5250 incorporates a negative voltage generator to operate with a single positive supply voltage from 3.3 V to 5 V applied to the VDD pin when the VSS pin is connected to ground. The negative voltage generator can be disabled when an external negative supply voltage of ?3.3 V is applied to the VSS pin. The ADRF5250 provides a 1.8 V logic-compatible, 3-pin control interface.Applications Cellular/4G infrastructure Wireless infrastructure Mobile radios Test equipment

The ADRF5300 is a reflective, SPDT switch manufactured in the silicon process.The ADRF5300 is developed for 5G applications ranging from 24 GHz to 32 GHz. The ADRF5300 has a low insertion loss of 1.1 dB, a high isolation of 38 dB, and an RF input power handling capability of 28 dBm average and 36 dBm peak.The ADRF5300 incorporates a negative voltage generator (NVG) to operate with a single positive supply of 3.3 V (VDD) applied to the VDD pin. The device employs CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5300 is packaged in a 20-terminal, 3 mm ? 3 mm, RoHS-compliant, land grid array (LGA) package and can operate from ?40?C to +105?C.APPLICATIONSIndustrial scannerTest instrumentationCellular infrastructure: 5G millimeter waveMilitary radios, radars, electronic counter measures (ECMs)Microwave radios and very small aperture terminals (VSATs)

The ADRF5547 is a dual-channel, integrated RF, front end multichip module designed for time division duplexing (TDD) applications that operates from 3.7 GHz to 5.3 GHz. The ADRF5547 is configured in dual channels with a cascading twostage low noise amplifier (LNA) and a high power silicon, single-pole, double-throw (SPDT) switch.In high gain mode, the cascaded, two-stage LNA and switch offer a low noise figure of 1.6 dB and high gain of 33 dB at 4.6 GHz with an output third order intercept point (OIP3) of 31 dBm (typical).In low gain mode, one stage of the two-stage LNAs is in bypass, providing 18 dB gain at lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.?In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.50 dB and handles long term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 40 dBm for full lifetime operation and 43 dBm for single event (<10 sec) LNA protection operation.The device comes in an RoHS compliant, compact, 40-lead, 6 mm ? 6 mm LFCSP.Applications? Wireless infrastructure TDD Massive Multiple input and Multiple Output (MIMO) and Active Antenna Systems TDD-based Communication Systems

The ADRF6650 is a highly integrated downconverter that integrates dual mixers, dual digital switched attenuators, dual digital variable gain amplifiers, a phase-locked loop (PLL), and voltage controlled oscillators (VCOs). In addition, the ADRF6650 integrates two radio frequency (RF) baluns, serial gain control (SGC) controls, and fast enable inputs for time division duplex (TDD) operation.The on-chip RF baluns enable the ADRF6650 to support 50 ? terminated RF inputs. The integrated passive mixer provides a highly linear downconversion for a 200 MHz, sliding, intermediate frequency (IF) window. The ADRF6650 uses broadband square wave limiting local oscillator (LO) amplifiers to achieve an RF bandwidth of 450 MHz to 2700 MHz. Unlike conventional narrow-band sine wave LO amplifier solutions, this amplifier permits the LO to be applied either above or below the RF input over an extremely wide bandwidth.The ADRF6650 offers two alternatives for generating the differential LO input signal: internally via the on-chip fractional-N synthesizer with low phase noise VCOs, or externally via a low phase noise LO signal. The integrated PLL/VCO enables continuous LO coverage from 450 MHz to 2900 MHz. The PLL referenceinput supports a wide frequency range and includes integrated reference dividers before the phase frequency detector (PFD).The ADRF6650 is fabricated using an advanced silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor(BiCMOS) process. It is available in a 56-lead, RoHS-compliant, 8 mm ? 8 mm, lead frame chip scale package (LFCSP) package with an exposed pad. Performance is specified over the ?40?C to +105?C maximum paddle temperature.Applications Multiband/multistandard cellular base station diversity receivers Wideband radio link diversity downconverters Multimode cellular extenders and picocells

The ADRF6780 is a silicon germanium (SiGe) design, wideband,microwave upconverter optimized for point to point microwaveradio designs operating in the 5.9 GHz to 23.6 GHz frequencyrange.The upconverter offers two modes of frequency translation. The device is capable of direct conversion to radio frequency (RF) from baseband I/Q input signals, as well as single sideband (SSB) upconversion from a real intermediate frequency (IF) input carrier frequency. The baseband inputs are high impedance and are generally terminated off chip with 100 ? differential back terminations. The baseband I/Q input path can be disabled and a modulated real IF signal anywhere from 0.8 GHz to 3.5 GHz can fed into the IF input path and upconverted to 5.9 GHz to 23.6 GHz while suppressing the unwanted sideband by typically better than 25 dBc. The serial port interface (SPI) allows tweaking of the quadrature phase adjustment to allow optimum sideband suppression. In addition, the SPI interface allows powering down the output power detector to reduce power consumption when power monitoring is not necessary.The ADRF6780 upconverter comes in a compact, thermallyenhanced, 5 mm ? 5 mm LFCSP package. The ADRF6780operates over the ?40?C to +85?C temperature range.APPLICATIONS Point to point microwave radios Radar, electronic warfare systems Instrumentation, automatic test equipment (ATE)

The ADRV9002 is a highly integrated RF transceiver that has dual-channel transmitters, dual-channel receivers, integrated synthesizers, and digital signal processing functions.The ADRV9002 is a high performance, highly linear, high dynamic range transceiver designed for performance vs. power consumption system optimization. The device is configurable and ideally suited to demanding, low power, portable and battery powered equipment. The ADRV9002 operates from 30 MHz to 6000 MHz and covers the UHF, VHF, industrial, scientific, and medical (ISM) bands, and cellular frequency bands in narrow-band (kHz) and wideband operation up to 40 MHz. The ADRV9002 is capable of both TDD and FDD operation.The transceiver consists of direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, which eliminate the need for these functions in the digital baseband. In addition, several auxiliary functions, such as auxiliary analog-to-digital converters (ADCs), auxiliary digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs), are integrated to provide additional monitoring and control capability.The fully integrated phase-locked loops (PLLs) provide high performance, low power, fractional-N frequency synthesis for the transmitter, receiver, and clock sections. Careful design and layout techniques provide the isolation required in high performance personal radio applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. The local oscillators (LOs) have flexible configuration options and include fast lock modes.The transceiver includes low power sleep and monitor modes to save power and extend the battery life of portable devices while monitoring communications.The fully integrated, low power digital predistortion (DPD) is optimized for both narrow-band and wideband signals and enables linearization of high efficiency power amplifiers.The ADRV9002 core can be powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard 4-wire serial port. Other voltage supplies are used to provide proper digital interface levels and to optimize the receiver, transmitter, and auxiliary converter performance.High data rate and low data rate interfaces are supported using configurable CMOS or low voltage differential signaling (LVDS) serial synchronous interface (SSI) choice.The ADRV9002 is packaged in a 12 mm ? 12 mm, 196-ball chip scale package ball grid array (CSP_BGA).APPLICATIONS Mission critical communications Very high frequency (VHF), ultrahigh frequency (UHF), and cellular to 6 GHz Time division duplexing (TDD) and frequency division duplexing (FDD) applications

The receive path consists of two independent, wide bandwidth (BW), direct conversion receivers with state-of-the-art dynamic range. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. RF front-end control and several auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) for the power amplifier (PA) are also integrated.In addition to automatic gain control (AGC), the ADRV9008-1 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time, sigma-delta (?-?) ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing relaxes the requirements of the RF filters compared to traditional intermediate frequency (IF) receivers.The fully integrated phase-locked loop (PLL) provides high per-formance, low power, fractional-N, RF synthesis for the receiver signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multi-chip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9008-1 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9008-1 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to mini-mize power consumption during normal use. The ADRV9008-1 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G FDD, macrocell base stations Wide band active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

The ADTR1107 is a compact, 6 GHz to 18 GHz, front-end IC?with an integrated power amplifier, low noise amplifier (LNA), and a reflective single-pole double-throw (SPDT) switch. These?integrated features make the device ideal for phased array antenna and radar applications. The front-end IC offers 25 dBm of saturated output power (PSAT) and 22?dB small signal gain in?transmit state, and 18 dB small signal gain and 2.5 dB noise figure in receive state. The device has a directional coupler for power detection. The input/outputs (I/Os) are internally matched to 50 ?. The ADTR1107 is supplied in a 5 mm ? 5 mm, 24-terminal, land grid array (LGA) package.Applications Phased array antenna Military radar Weather radar Communication links Electronic warfare

The HMC686LP4(E) is a high dynamic range passive MMIC mixer with integrated LO amplifier in a 4x4 SMT QFN package covering 0.7 to 1.1 GHz. Excellent input IP3 performance of +34 dBm for down conversion is provided for 3G & 4G GSM/CDMA applications at an LO drive of 0 dBm. With an input 1 dB compression of +25 dBm, the RF port will accept a wide range of input signal levels. Conversion loss is 7.5 dB typical. The DC to 500 MHz IF frequency response will satisfy GSM/CDMA transmit or receive frequency plans.The HMC686LP4(E) is optimized to high side LO frequency plans for 0.7 - 1.1 GHz RF Band and is pin for pin compatible with the?HMC684LP4(E)?which is a 0.7 - 1.0 GHz converter optimized for low side LO. The HMC686LP4(E) is optimized to low side LO frequency plans for 1.4 - 1.5 GHz RF LTE band applications.APPLICATIONS Cellular/3G & LTE/WiMAX/4G Basestations & Repeaters GSM, CDMA & OFDM Transmitters and Receivers

The HMC822LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO with a triband output, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios